» UW Architecture Publications Classified by Faculty

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Goodman

• James R. Goodman and Wei-Chung Hsu. Author retrospective for code scheduling and register allocation in large basic blocks. In ACM International Conference on Supercomputing 25th Anniversary Volume, pp. 4-5, ACM, 2014.
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• Fuad Tabba, Andrew W. Hay, and James R. Goodman. Transactional conflict decoupling and value prediction. In Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31 - June 04, 2011, pp. 33-42, ACM, 2011.
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• Fuad Tabba, Mark Moir, James R. Goodman, Andrew W. Hay, and Cong Wang. NZTM: nonblocking zero-indirection transactional memory. In SPAA 2009: Proceedings of the 21st Annual ACM Symposium on Parallelism in Algorithms and Architectures, Calgary, Alberta, Canada, August 11-13, 2009, pp. 204-213, ACM, 2009.
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• Doug Burger and James R. Goodman. Billion-Transistor Architectures: There and Back Again. Computer, 37(3):22-28, 2004.
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• Ravi Rajwar, Alain Kägi, and James R. Goodman. Inferential Queueing and Speculative Push. Int. J. Parallel Program., 32(3):225-258, 2004.
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• Andrew S. Tanenbaum and James R. Goodman. Computerarchitektur - Strukturen, Konzepte, Grundlagen, 4. Auflage, Pearson Studium, 2004.
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• Ravi Rajwar and James R. Goodman. Transactional Execution: Toward Reliable, High-Performance Multithreading. IEEE Micro, 23(6):117-125, 2003.
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• Ravi Rajwar, Alain Kägi, and James R. Goodman. Inferential queueing and speculative push for reducing critical communication latencies. In Proceedings of the 17th Annual International Conference on Supercomputing, ICS 2003, San Francisco, CA, USA, June 23-26, 2003, pp. 273-284, ACM, 2003.
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• Ravi Rajwar and James R. Goodman. Transactional lock-free execution of lock-based programs. In Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), San Jose, California, USA, October 5-9, 2002, pp. 5-17, ACM Press, 2002.
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• Ravi Rajwar and James R. Goodman. Speculative lock elision: enabling highly concurrent multithreaded execution. In Proceedings of the 34th Annual International Symposium on Microarchitecture, Austin, Texas, USA, December 1-5, 2001, pp. 294-305, ACM/IEEE Computer Society, 2001.
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• Andrew S. Tanenbaum and James R. Goodman. Computerarchitektur - Strukturen, Konzepte, Grundlagen, 4. Auflage, Pearson Studium, 2001.
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• Ravi Rajwar, Alain Kägi, and James R. Goodman. Improving the Throughput of Synchronization by Insertion of Delays. In Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, Toulouse, France, January 8-12, 2000, pp. 168-179, IEEE Computer Society, 2000.
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• Stefanos Kaxiras, Doug Burger, and James R. Goodman. DataScalar: A memory-centric approach to computing. J. Syst. Archit., 45(12-13):1001-1022, 1999.
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• Stefanos Kaxiras and James R. Goodman. Improving CC-NUMA Performance Using Instruction-Based Prediction. In Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, Orlando, FL, USA, January 9-12, 1999, pp. 161-170, IEEE Computer Society, 1999.
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• James R. Goodman. Retrospective: Using Cache Memory to Reduce Processor-Memory Traffic. In 25 Years of the International Symposia on Computer Architecture (Selected Papers), pp. 32-33, ACM, 1998.
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• James R. Goodman. Using Cache Memory to Reduce Processor-Memory Traffic. In 25 Years of the International Symposia on Computer Architecture (Selected Papers), pp. 255-262, ACM, 1998.
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• Stefanos Kaxiras, Stein Gjessing, and James R. Goodman. A Study of Three Dynamic Approaches to Handle Widely Shared Data in Shared-memory Multiprocessors. In Proceedings of the 12th international conference on Supercomputing, ICS 1998, Melbourne, Australia, July 13-17, 1998, pp. 457-464, ACM, 1998.
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• Doug Burger, James R. Goodman, and Gurindar S. Sohi. Memory Systems. In Allen B. Tucker, editors, The Computer Science and Engineering Handbook, pp. 447-461, CRC Press, 1997.
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• Doug Burger and James R. Goodman. Billion-Transistor Architectures - Guest Editors' Introduction. Computer, 30(9):46-49, 1997.
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• Doug Burger, James R. Goodman, and Alain Kägi. Limited bandwidth to affect processor design. IEEE Micro, 17(6):55-62, 1997.
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• Doug Burger, Stefanos Kaxiras, and James R. Goodman. DataScalar Architectures. In Proceedings of the 24th International Symposium on Computer Architecture, Denver, Colorado, USA, June 2-4, 1997, pp. 338-349, ACM, 1997.
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• Alain Kägi, Doug Burger, and James R. Goodman. Efficient Synchronization: Let Them Eat QOLB. In Proceedings of the 24th International Symposium on Computer Architecture, Denver, Colorado, USA, June 2-4, 1997, pp. 170-180, ACM, 1997.
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• Doug Burger, James R. Goodman, and Alain Kägi. Memory Bandwidth Limitations of Future Microprocessors. In Proceedings of the 23rd Annual International Symposium on Computer Architecture, Philadelphia, PA, USA, May 22-24, 1996, pp. 78-89, ACM, 1996.
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• Stefanos Kaxiras and James R. Goodman. The GLOW Cache Coherence Protocol Extensions for Widely Shared Data. In Proceedings of the 10th international conference on Supercomputing, ICS 1996, Philadelphia, PA, USA, May 25-28, 1996, pp. 35-43, ACM, 1996.
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• Alain Kägi, Nagi Aboulenein, Doug Burger, and James R. Goodman. Techniques for Reducing Overheads of Shared-Memory Multiprocessing. In Proceedings of the 9th international conference on Supercomputing, ICS 1995, Barcelona, Spain, July 3-7, 1995, pp. 11-20, ACM, 1995.
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• Nagi Aboulenein, James R. Goodman, Stein Gjessing, and Philip J. Woest. Hardware Support for Synchronization in the Scalable Coherent Interface (SCI). In Proceedings of the 8th International Symposium on Parallel Processing, Cancún, Mexico, April 1994, pp. 141-150, IEEE Computer Society, 1994.
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• Steven L. Scott and James R. Goodman. The Impact of Pipelined Channels on k-ary n-Cube Networks. IEEE Trans. Parallel Distributed Syst., 5(1):2-16, 1994.
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• Steven L. Scott and James R. Goodman. Performance of Pruning-Cache Directories for Large-Scale Multiprocessors. IEEE Trans. Parallel Distributed Syst., 4(5):520-534, 1993.
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• Ross E. Johnson and James R. Goodman. Synthesizing General Topologies from Rings. In Proceedings of the 1992 International Conference on Parallel Processing, University of Michigan, An Arbor, Michigan, USA, August 17-21, 1992. Volume I: Architecture, pp. 86-95, CRC Press, 1992.
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• Steven L. Scott, James R. Goodman, and Mary K. Vernon. Performance of the SCI Ring. In Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, Australia, May 1992, pp. 403-414, ACM, 1992.
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• Howard Jay Siegel, Seth Abraham, William L. Bain, Kenneth E. Batcher, Thomas L. Casavant, Doug DeGroot, Jack B. Dennis, David C. Douglas, Tse-Yun Feng, James R. Goodman, Alan Huang, Harry F. Jordan, J. Robert Jamp, Yale N. Patt, Alan Jay Smith, James E. Smith, Lawrence Snyder, Harold S. Stone, Russ Tuck, and Benjamin W. Wah. Report of the Purdue Workshop on Grand Challenges in Computer Architecture for the Support of High Performance Computing. J. Parallel Distributed Comput., 16(3):199-211, 1992.
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• James R. Goodman, Mary K. Vernon, and Philip J. Woest. Efficent Synchronization Primitives for Large-Scale Cache-Coherent Multiprocessors. In ASPLOS-III Proceedings - Third International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, USA, April 3-6, 1989, pp. 64-75, ACM Press, 1989.
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• Wei-Chung Hsu, Charles N. Fischer, and James R. Goodman. On the Minimization of Loads/Stores in Local Register Allocation. IEEE Trans. Software Eng., 15(10):1252-1260, 1989.
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• Gurindar S. Sohi, James E. Smith, and James R. Goodman. Restricted Fetch\&Phi operations for parallel processing. In Proceedings of the 3rd international conference on Supercomputing, ICS 1989, Heraklion, Crete, Greece, June 5-9, 1989, pp. 410-416, ACM, 1989.
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• James R. Goodman. Reply to David R. Cheriton's, Pat Boyle's, and Gert A. Slavenburg's "Comments on 'Coherency for multiprocessor virtual addressed caches' by James R. Goodman". SIGARCH Comput. Archit. News, 16(3):7, 1988.
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• James R. Goodman and Wei-Chung Hsu. Code scheduling and register allocation in large basic blocks. In Proceedings of the 2nd international conference on Supercomputing, ICS 1988, Saint Malo, France, July 4-8, 1988, pp. 442-452, ACM, 1988.
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• James R. Goodman and Philip J. Woest. The Wisconsin Multicube: A New Large-Scale Cache-Coherent Multiprocessor. In Proceedings of the 15th Annual International Symposium on Computer Architecture, Honolulu, Hawaii, USA, May-June 1988, pp. 422-431, IEEE Computer Society, 1988.
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• James R. Goodman. Coherency for Multiprocessor Virtual Address Caches. In Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), Palo Alto, California, USA, October 5-8, 1987, pp. 72-81, ACM Press, 1987.
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• Andrew R. Pleszkun, James R. Goodman, Wei-Chung Hsu, R. T. Joersz, George E. Bier, Philip J. Woest, and P. B. Schechter. WISQ: A Restartable Architecture Using Queues. In Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh, PA, USA, June 1987, pp. 290-299, 1987.
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• James R. Goodman and Honesty C. Young. Comments on "A Massive Memory Machine". IEEE Trans. Computers, 35(10):907-910, 1986.
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• James R. Goodman and Wei-Chung Hsu. On the Use of Registers vs. Cache to Minimize Memory Traffic. In Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, pp. 375-383, IEEE Computer Society, 1986.
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• Honesty C. Young and James R. Goodman. The Design of a Queue-Based Vector Supercomputer. In International Conference on Parallel Processing, ICPP'86, University Park, PA, USA, August 1986, pp. 483-486, IEEE Computer Society Press, 1986.
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• James R. Goodman, Jian-tu Hsieh, Koujuch Liou, Andrew R. Pleszkun, P. B. Schechter, and Honesty C. Young. PIPE: A VLSI Decoupled Architecture. In Proceedings of the 12th Annual Symposium on Computer Architecture, Boston, MA, USA, June 1985, pp. 20-27, IEEE Computer Society, 1985.
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• James E. Smith and James R. Goodman. Instruction Cache Replacement Policies and Organizations. IEEE Trans. Computers, 34(3):234-241, 1985.
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• James R. Goodman and MenChow Chiang. The Use of Static Column RAM as a Memory Hierarchy. In Proceedings of the 11th Annual Symposium on Computer Architecture, Ann Arbor, USA, June 1984, pp. 167-174, ACM, 1984.
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• James R. Goodman. Using Cache Memory to Reduce Processor-Memory Traffic. In Proceedings of the 10th Annual Symposium on Computer Architecture, 1983, pp. 124-131, ACM, 1983.
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• James E. Smith and James R. Goodman. A Study of Instruction Cache Organizations and Replacement Policies. In Proceedings of the 10th Annual Symposium on Computer Architecture, 1983, pp. 132-137, ACM, 1983.
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• Chinya V. Ravishankar and James R. Goodman. VLSI Considerations that Influence Data Flow Architecture. In COMPCON'82, Digest of Papers, Twenty-Fourth IEEE Computer Society International Conference, San Francisco, California, USA, February 22-25, 1982, pp. 228-232, IEEE Computer Society, 1982.
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• James R. Goodman and Carlo H. Séquin. Hypertree: A Multiprocessor Interconnection Topology. IEEE Trans. Computers, 30(12):923-933, 1981.
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• Chittoor V. Ramamoorthy, James R. Goodman, and K. H. Kim. Some Properties of Iterative Square-Rooting Methods Using High-Speed Multiplication. IEEE Trans. Computers, 21(8):837-847, 1972.
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Hill

• Thomas M. Conte, Ian T. Foster, William Gropp, and Mark D. Hill. Advancing Computing's Foundation of US Industry \& Society. CoRR, abs/2101.01284, 2021.
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• Ian T. Foster, Daniel Lopresti, Bill Gropp, Mark D. Hill, and Katie Schuman. A National Discovery Cloud: Preparing the US for Global Competitiveness in the New Era of 21st Century Digital Transformation. CoRR, abs/2104.06953, 2021.
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• Todd Hylton, Thomas M. Conte, and Mark D. Hill. A vision to compute like nature: thermodynamically. Commun. ACM, 64(6):35-38, 2021.
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• Randy Bryant, Mark D. Hill, Tom Kazior, Daniel Lee, Jie Liu, Klara Nahrstedt, Vijay Narayanan, Jan M. Rabaey, Hava T. Siegelmann, Naresh R. Shanbhag, Naveen Verma, and H.-S. Philip Wong. Nanotechnology-inspired Information Processing Systems of the Future. CoRR, abs/2005.02434, 2020.
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• Gregory D. Hager, Mark D. Hill, and Katherine A. Yelick. Opportunities and Challenges for Next Generation Computing. CoRR, abs/2008.00023, 2020.
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• Swapnil Haria, Mark D. Hill, and Michael M. Swift. MOD: Minimally Ordered Durable Datastructures for Persistent Memory. In ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, March 16-20, 2020, pp. 775-788, ACM, 2020.
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• Mark D. Hill. Technical perspective: Why 'correct' computers can leak your information. Commun. ACM, 63(7):92, 2020.
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• Vijay Nagarajan, Daniel J. Sorin, Mark D. Hill, and David A. Wood. A Primer on Memory Consistency and Cache Coherence, Second Edition, Synthesis Lectures on Computer Architecture, Morgan \& Claypool Publishers, 2020.
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• Tom Conte, Erik DeBenedictis, Natesh Ganesh, Todd Hylton, John Paul Strachan, R. Stanley Williams, Alexander Alemi, Lee Altenberg, Gavin E. Crooks, James P. Crutchfield, Lídia del Rio, Josh Deutsch, Michael Robert DeWeese, Khari Douglas, Massimiliano Esposito, Michael P. Frank, Robert Fry, Peter Harsha, Mark D. Hill, Christopher T. Kello, Jeff Krichmar, Suhas Kumar, Shih-Chii Liu, Seth Lloyd, Matteo Marsili, Ilya Nemenman, Alex Nugent, Norman Packard, Dana Randall, Peter Sadowski, Narayana Santhanam, Robert Shaw, Adam Z. Stieg, Elan Stopnitzky, Christof Teuscher, Chris Watkins, David Wolpert, J. Joshua Yang, and Yan Yufik. Thermodynamic Computing. CoRR, abs/1911.01968, 2019.
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• Swapnil Haria, Mark D. Hill, and Michael M. Swift. MOD: Minimally Ordered Durable Datastructures for Persistent Memory. CoRR, abs/1908.11850, 2019.
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• Mark D. Hill, Jon Masters, Parthasarathy Ranganathan, Paul Turner, and John L. Hennessy. On the Spectre and Meltdown Processor Security Vulnerabilities. IEEE Micro, 39(2):9-19, 2019.
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• Mark D. Hill. Reflections and Research Advice Upon Receiving the 2019 Eckert-Mauchly Award. IEEE Micro, 39(5):119-124, 2019.
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• Mark D. Hill and Vijay Janapa Reddi. Gables: A Roofline Model for Mobile SoCs. In 25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019, Washington, DC, USA, February 16-20, 2019, pp. 317-330, IEEE, 2019.
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• Mark D. Hill. Three Other Models of Computer System Performance. CoRR, abs/1901.02926, 2019.
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• Mark D. Hill and Vijay Janapa Reddi. Accelerator-level Parallelism. CoRR, abs/1907.02064, 2019.
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• Pratyush Mahapatra, Mark D. Hill, and Michael M. Swift. Don't Persist All : Efficient Persistent Data Structures. CoRR, abs/1905.13011, 2019.
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• Swapnil Haria, Mark D. Hill, and Michael M. Swift. Devirtualizing Memory in Heterogeneous Systems. In Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2018, Williamsburg, VA, USA, March 24-28, 2018, pp. 637-650, ACM, 2018.
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• Luis Ceze, Mark D. Hill, Karthikeyan Sankaralingam, and Thomas F. Wenisch. Democratizing Design for Future Computing Platforms. CoRR, abs/1706.08597, 2017.
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• Thomas M. Conte, Erik P. DeBenedictis, R. Stanley Williams, and Mark D. Hill. Challenges to Keeping the Computer Industry Centered in the US. CoRR, abs/1706.10267, 2017.
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• Jayneel Gandhi, Mark D. Hill, and Michael M. Swift. Agile Paging for Efficient Memory Virtualization. IEEE Micro, 37(3):80-86, 2017.
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• Mark D. Hill and Michael R. Marty. Retrospective on Amdahl's Law in the Multicore Era. Computer, 50(6):12-14, 2017.
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• Vasant G. Honavar, Katherine A. Yelick, Klara Nahrstedt, Holly E. Rushmeier, Jennifer Rexford, Mark D. Hill, Elizabeth Bradley, and Elizabeth D. Mynatt. Advanced Cyberinfrastructure for Science, Engineering, and Public Policy. CoRR, abs/1707.00599, 2017.
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• Sanketh Nalli, Swapnil Haria, Mark D. Hill, Michael M. Swift, Haris Volos, and Kimberly Keeton. An Analysis of Persistent Memory Use with WHISPER. In Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2017, Xi'an, China, April 8-12, 2017, pp. 135-148, ACM, 2017.
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• Lena E. Olson, Mark D. Hill, and David A. Wood. Crossing Guard: Mediating Host-Accelerator Coherence Interactions. In Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2017, Xi'an, China, April 8-12, 2017, pp. 163-176, ACM, 2017.
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• Luis Ceze, Mark D. Hill, and Thomas F. Wenisch. Arch2030: A Vision of Computer Architecture Research over the Next 15 Years. CoRR, abs/1612.03182, 2016.
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• Jayneel Gandhi, Vasileios Karakostas, Furkan Ayar, Adrián Cristal, Mark D. Hill, Kathryn S. McKinley, Mario Nemirovsky, Michael M. Swift, and Osman S. Unsal. Range Translations for Fast Virtual Memory. IEEE Micro, 36(3):118-126, 2016.
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• Jayneel Gandhi, Mark D. Hill, and Michael M. Swift. Agile Paging: Exceeding the Best of Nested and Shadow Paging. In 43rd ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2016, Seoul, South Korea, June 18-22, 2016, pp. 707-718, IEEE Computer Society, 2016.
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• Mark D. Hill, Sarita V. Adve, Luis Ceze, Mary Jane Irwin, David R. Kaeli, Margaret Martonosi, Josep Torrellas, Thomas F. Wenisch, David A. Wood, and Katherine A. Yelick. 21st Century Computer Architecture. CoRR, abs/1609.06756, 2016.
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• Mark D. Hill, Dave Christie, David A. Patterson, Joshua J. Yi, Derek Chiou, and Resit Sendag. Proprietary versus Open Instruction Sets. IEEE Micro, 36(4):58-68, 2016.
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• Vasant G. Honavar, Mark D. Hill, and Katherine A. Yelick. Accelerating Science: A Computing Research Agenda. CoRR, abs/1604.02006, 2016.
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• Vasileios Karakostas, Jayneel Gandhi, Adrián Cristal, Mark D. Hill, Kathryn S. McKinley, Mario Nemirovsky, Michael M. Swift, and Osman S. Unsal. Energy-efficient address translation. In 2016 IEEE International Symposium on High Performance Computer Architecture, HPCA 2016, Barcelona, Spain, March 12-16, 2016, pp. 631-643, IEEE Computer Society, 2016.
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• Jason Lowe-Power, Mark D. Hill, and David A. Wood. When to use 3D Die-Stacked Memory for Bandwidth-Constrained Big Data Workloads. CoRR, abs/1608.07485, 2016.
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• Lena E. Olson, Simha Sethumadhavan, and Mark D. Hill. Security Implications of Third-Party Accelerators. IEEE Comput. Archit. Lett., 15(1):50-53, 2016.
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• Lena E. Olson and Mark D. Hill. Probabilistic Directed Writebacks for Exclusive Caches. SIGARCH Comput. Archit. News, 44(1):9-18, 2016.
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• Vasileios Karakostas, Jayneel Gandhi, Furkan Ayar, Adrián Cristal, Mark D. Hill, Kathryn S. McKinley, Mario Nemirovsky, Michael M. Swift, and Osman S. Unsal. Redundant memory mappings for fast access to large memories. In Proceedings of the 42nd Annual International Symposium on Computer Architecture, Portland, OR, USA, June 13-17, 2015, pp. 66-78, ACM, 2015.
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• Lena E. Olson, Jason Power, Mark D. Hill, and David A. Wood. Border control: sandboxing accelerators. In Proceedings of the 48th International Symposium on Microarchitecture, MICRO 2015, Waikiki, HI, USA, December 5-9, 2015, pp. 470-481, ACM, 2015.
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• Marc S. Orr, Shuai Che, Ayse Yilmazer, Bradford M. Beckmann, Mark D. Hill, and David A. Wood. Synchronization Using Remote-Scope Promotion. In Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2015, Istanbul, Turkey, March 14-18, 2015, pp. 73-86, ACM, 2015.
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• Jason Power, Joel Hestness, Marc S. Orr, Mark D. Hill, and David A. Wood. gem5-gpu: A Heterogeneous CPU-GPU Simulator. IEEE Comput. Archit. Lett., 14(1):34-36, 2015.
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• Jason Power, Yinan Li, Mark D. Hill, Jignesh M. Patel, and David A. Wood. Implications of Emerging 3D GPU Architecture on the Scan Primitive. SIGMOD Rec., 44(1):18-23, 2015.
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• Jason Power, Yinan Li, Mark D. Hill, Jignesh M. Patel, and David A. Wood. Toward GPUs being mainstream in analytic processing: An initial argument using simple scan-aggregate queries. In Proceedings of the 11th International Workshop on Data Management on New Hardware, DaMoN 2015, Melbourne, VIC, Australia, May 31 - June 04, 2015, pp. 11:1-11:8, ACM, 2015.
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• Jayneel Gandhi, Arkaprava Basu, Mark D. Hill, and Michael M. Swift. BadgerTrap: a tool to instrument x86-64 TLB misses. SIGARCH Comput. Archit. News, 42(2):20-23, 2014.
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• Jayneel Gandhi, Arkaprava Basu, Mark D. Hill, and Michael M. Swift. Efficient Memory Virtualization: Reducing Dimensionality of Nested Page Walks. In 47th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2014, Cambridge, United Kingdom, December 13-17, 2014, pp. 178-189, IEEE Computer Society, 2014.
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• Blake A. Hechtman, Shuai Che, Derek R. Hower, Yingying Tian, Bradford M. Beckmann, Mark D. Hill, Steven K. Reinhardt, and David A. Wood. QuickRelease: A throughput-oriented approach to release consistency on GPUs. In 20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014, Orlando, FL, USA, February 15-19, 2014, pp. 189-200, IEEE Computer Society, 2014.
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• Mark D. Hill. 21st century computer architecture keynote at 2014 international conference on supercomputing (ICS). In 2014 International Conference on Supercomputing, ICS'14, Muenchen, Germany, June 10-13, 2014, pp. 123, ACM, 2014.
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• Mark D. Hill. 21st century computer architecture. In ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP '14, Orlando, FL, USA, February 15-19, 2014, pp. 1-2, ACM, 2014.
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• Derek R. Hower, Blake A. Hechtman, Bradford M. Beckmann, Benedict R. Gaster, Mark D. Hill, Steven K. Reinhardt, and David A. Wood. Heterogeneous-race-free memory models. In Architectural Support for Programming Languages and Operating Systems, ASPLOS 2014, Salt Lake City, UT, USA, March 1-5, 2014, pp. 427-440, ACM, 2014.
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• Jason Power, Mark D. Hill, and David A. Wood. Supporting x86-64 address translation for 100s of GPU lanes. In 20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014, Orlando, FL, USA, February 15-19, 2014, pp. 568-578, IEEE Computer Society, 2014.
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• Arkaprava Basu, Derek Hower, Mark D. Hill, and Michael M. Swift. FreshCache: Statically and dynamically exploiting dataless ways. In 2013 IEEE 31st International Conference on Computer Design, ICCD 2013, Asheville, NC, USA, October 6-9, 2013, pp. 286-293, IEEE Computer Society, 2013.
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• Arkaprava Basu, Jayneel Gandhi, Jichuan Chang, Mark D. Hill, and Michael M. Swift. Efficient virtual memory for big memory servers. In The 40th Annual International Symposium on Computer Architecture, ISCA'13, Tel-Aviv, Israel, June 23-27, 2013, pp. 237-248, ACM, 2013.
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• Mark D. Hill. Research directions for 21st century computer systems: asplos 2013 panel. In Architectural Support for Programming Languages and Operating Systems, ASPLOS 2013, Houston, TX, USA, March 16-20, 2013, pp. 459-460, ACM, 2013.
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• Jason Power, Arkaprava Basu, Junli Gu, Sooraj Puthoor, Bradford M. Beckmann, Mark D. Hill, Steven K. Reinhardt, and David A. Wood. Heterogeneous system coherence for integrated CPU-GPU systems. In The 46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-46, Davis, CA, USA, December 7-11, 2013, pp. 457-467, ACM, 2013.
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• Arkaprava Basu, Mark D. Hill, and Michael M. Swift. Reducing memory reference energy with opportunistic virtual caching. In 39th International Symposium on Computer Architecture (ISCA 2012), June 9-13, 2012, Portland, OR, USA, pp. 297-308, IEEE Computer Society, 2012.
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• Gabriel H. Loh and Mark D. Hill. Supporting Very Large DRAM Caches with Compound-Access Scheduling and MissMap. IEEE Micro, 32(3):70-78, 2012.
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• Milo M. K. Martin, Mark D. Hill, and Daniel J. Sorin. Why on-chip cache coherence is here to stay. Commun. ACM, 55(7):78-89, 2012.
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• Arkaprava Basu, Jayaram Bobba, and Mark D. Hill. Karma: scalable deterministic record-replay. In Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31 - June 04, 2011, pp. 359-368, ACM, 2011.
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• Nathan L. Binkert, Bradford M. Beckmann, Gabriel Black, Steven K. Reinhardt, Ali G. Saidi, Arkaprava Basu, Joel Hestness, Derek Hower, Tushar Krishna, Somayeh Sardashti, Rathijit Sen, Korey Sewell, Muhammad Shoaib Bin Altaf, Nilay Vaish, Mark D. Hill, and David A. Wood. The gem5 simulator. SIGARCH Comput. Archit. News, 39(2):1-7, 2011.
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• Jayaram Bobba, Marc Lupon, Mark D. Hill, and David A. Wood. Safe and efficient supervised memory systems. In 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), February 12-16 2011, San Antonio, Texas, USA, pp. 369-380, IEEE Computer Society, 2011.
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• Derek Hower, Polina Dudnik, Mark D. Hill, and David A. Wood. Calvin: Deterministic or not? Free will to choose. In 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), February 12-16 2011, San Antonio, Texas, USA, pp. 333-334, IEEE Computer Society, 2011.
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• Gabriel H. Loh and Mark D. Hill. Efficiently enabling conventional block sizes for very large die-stacked DRAM caches. In 44rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2011, Porto Alegre, Brazil, December 3-7, 2011, pp. 454-464, ACM, 2011.
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• Daniel J. Sorin, Mark D. Hill, and David A. Wood. A Primer on Memory Consistency and Cache Coherence, Synthesis Lectures on Computer Architecture, Morgan \& Claypool Publishers, 2011.
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• Jayaram Bobba, Weiwei Xiong, Luke Yen, Mark D. Hill, and David A. Wood. StealthTest: Low Overhead Online Software Testing Using Transactional Memory. In PACT 2009, Proceedings of the 18th International Conference on Parallel Architectures and Compilation Techniques, 12-16 September 2009, Raleigh, North Carolina, USA, pp. 146-155, IEEE Computer Society, 2009.
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• Mark D. Hill. Opportunities beyond single-core microprocessors. In Proceedings of the 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2009, Raleigh, NC, USA, February 14-18, 2009, pp. 97, ACM, 2009.
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• Derek Hower, Pablo Montesinos, Luis Ceze, Mark D. Hill, and Josep Torrellas. Two hardware-based approaches for deterministic multiprocessor replay. Commun. ACM, 52(6):93-100, 2009.
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• Jayaram Bobba, Kevin E. Moore, Haris Volos, Luke Yen, Mark D. Hill, Michael M. Swift, and David A. Wood. Performance Pathologies in Hardware Transactional Memory. IEEE Micro, 28(1):32-41, 2008.
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• Jayaram Bobba, Neelam Goyal, Mark D. Hill, Michael M. Swift, and David A. Wood. TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory. In 35th International Symposium on Computer Architecture (ISCA 2008), June 21-25, 2008, Beijing, China, pp. 127-138, IEEE Computer Society, 2008.
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• Eric L. Hill, Mikko H. Lipasti, and Kewal K. Saluja. An accurate flip-flop selection technique for reducing logic SER. In The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings, pp. 128-136, IEEE Computer Society, 2008.
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• Mark D. Hill and Michael R. Marty. Amdahl's Law in the Multicore Era. Computer, 41(7):33-38, 2008.
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• Mark D. Hill. Is transactional memory an oxymoron?. Proc. VLDB Endow., 1(1):1, 2008.
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• Mark D. Hill. Amdahl's Law in the multicore era. In 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 16-20 February 2008, Salt Lake City, UT, USA, pp. 187, IEEE Computer Society, 2008.
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• Derek Hower and Mark D. Hill. Rerun: Exploiting Episodes for Lightweight Memory Race Recording. In 35th International Symposium on Computer Architecture (ISCA 2008), June 21-25, 2008, Beijing, China, pp. 265-276, IEEE Computer Society, 2008.
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• Michael R. Marty and Mark D. Hill. Virtual Hierarchies. IEEE Micro, 28(1):99-109, 2008.
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• Luke Yen, Stark C. Draper, and Mark D. Hill. Notary: Hardware techniques to enhance signatures. In 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy, pp. 234-245, IEEE Computer Society, 2008.
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• Jayaram Bobba, Kevin E. Moore, Haris Volos, Luke Yen, Mark D. Hill, Michael M. Swift, and David A. Wood. Performance pathologies in hardware transactional memory. In 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 81-91, ACM, 2007.
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• Joel S. Emer, Mark D. Hill, Yale N. Patt, Joshua J. Yi, Derek Chiou, and Resit Sendag. Single-Threaded vs. Multithreaded: Where Should We Focus?. IEEE Micro, 27(6):14-24, 2007.
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• Eric L. Hill and Mikko H. Lipasti. Transparent mode flip-flops for collapsible pipelines. In 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 553-560, IEEE, 2007.
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• Mark D. Hill, Derek Hower, Kevin E. Moore, Michael M. Swift, Haris Volos, and David A. Wood. A Case for Deconstructing Hardware Transactional Memory Systems. In Programming Models for Ubiquitous Parallelism, 02.09. - 07.09.2007, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany, 2007.
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• Michael R. Marty and Mark D. Hill. Virtual hierarchies to support server consolidation. In 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 46-56, ACM, 2007.
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• Daniel Sánchez, Luke Yen, Mark D. Hill, and Karthikeyan Sankaralingam. Implementing Signatures for Transactional Memory. In 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 1-5 December 2007, Chicago, Illinois, USA, pp. 123-133, IEEE Computer Society, 2007.
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• Min Xu, Rastislav Bodík, and Mark D. Hill. A Hardware Memory Race Recorder for Deterministic Replay. IEEE Micro, 27(1):48-55, 2007.
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• Luke Yen, Jayaram Bobba, Michael R. Marty, Kevin E. Moore, Haris Volos, Mark D. Hill, Michael M. Swift, and David A. Wood. LogTM-SE: Decoupling Hardware Transactional Memory from Caches. In 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 10-14 February 2007, Phoenix, Arizona, USA, pp. 261-272, IEEE Computer Society, 2007.
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• Eric L. Hill and Mikko H. Lipasti. Stall cycle redistribution in a transparent fetch pipeline. In Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 31-36, ACM, 2006.
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• Mark D. Hill, Jean-Luc Gaudiot, Mary W. Hall, Joe Marks, Paolo Prinetto, and Donna Baglio. A Wiki for discussing and promoting best practices in research. Commun. ACM, 49(9):63-64, 2006.
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• Natalie D. Enright Jerger, Eric L. Hill, and Mikko H. Lipasti. Friendly fire: understanding the effects of multiprocessor prefetches. In 2006 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2006, March 19-21, 2006, Austin, Texas, USA, Proceedings, pp. 177-188, IEEE Computer Society, 2006.
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• Michael R. Marty and Mark D. Hill. Coherence Ordering for Ring-based Chip Multiprocessors. In 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 9-13 December 2006, Orlando, Florida, USA, pp. 309-320, IEEE Computer Society, 2006.
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• Kevin E. Moore, Jayaram Bobba, Michelle J. Moravan, Mark D. Hill, and David A. Wood. LogTM: log-based transactional memory. In 12th International Symposium on High-Performance Computer Architecture, HPCA-12 2006, Austin, Texas, USA, February 11-15, 2006, pp. 254-265, IEEE Computer Society, 2006.
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• Michelle J. Moravan, Jayaram Bobba, Kevin E. Moore, Luke Yen, Mark D. Hill, Ben Liblit, Michael M. Swift, and David A. Wood. Supporting nested transactional memory in logTM. In Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2006, San Jose, CA, USA, October 21-25, 2006, pp. 359-370, ACM, 2006.
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• Min Xu, Mark D. Hill, and Rastislav Bodík. A regulated transitive reduction (RTR) for longer memory race recording. In Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2006, San Jose, CA, USA, October 21-25, 2006, pp. 49-60, ACM, 2006.
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• Milo M. K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, and David A. Wood. Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset. SIGARCH Comput. Archit. News, 33(4):92-99, 2005.
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• Michael R. Marty, Jesse D. Bingham, Mark D. Hill, Alan J. Hu, Milo M. K. Martin, and David A. Wood. Improving Multiple-CMP Systems Using Token Coherence. In 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 12-16 February 2005, San Francisco, CA, USA, pp. 328-339, IEEE Computer Society, 2005.
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• Min Xu, Rastislav Bodík, and Mark D. Hill. A serializability violation detector for shared-memory server programs. In Proceedings of the ACM SIGPLAN 2005 Conference on Programming Language Design and Implementation, Chicago, IL, USA, June 12-15, 2005, pp. 1-14, ACM, 2005.
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• Brian A. Fields, Rastislav Bodík, Mark D. Hill, and Chris J. Newburn. Interaction Cost: For When Event Counts Just Don't Add Up. IEEE Micro, 24(6):57-61, 2004.
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• Brian A. Fields, Rastislav Bodík, Mark D. Hill, and Chris J. Newburn. Interaction cost and shotgun profiling. ACM Trans. Archit. Code Optim., 1(3):272-304, 2004.
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• Mark D. Hill. A Future of Parallel Computer Architectures. In 33rd International Conference on Parallel Processing (ICPP 2004), 15-18 August 2004, Montreal, Quebec, Canada, pp. 2, IEEE Computer Society, 2004.
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• Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, and David A. Wood. Using Speculation to Simplify Multiprocessor Design. In 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, IEEE Computer Society, 2004.
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• Alaa R. Alameldeen, Milo M. K. Martin, Carl J. Mauer, Kevin E. Moore, Min Xu, Mark D. Hill, David A. Wood, and Daniel J. Sorin. Simulating a \textdollar2M Commercial Server on a \textdollar2K PC. Computer, 36(2):50-57, 2003.
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• Brian A. Fields, Rastislav Bodík, Mark D. Hill, and Chris J. Newburn. Using Interaction Costs for Microarchitectural Bottleneck Analysis. In Proceedings of the 36th Annual International Symposium on Microarchitecture, San Diego, CA, USA, December 3-5, 2003, pp. 228-242, IEEE Computer Society, 2003.
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• Milo M. K. Martin, Mark D. Hill, and David A. Wood. Token Coherence: A New Framework for Shared-Memory Multiprocessors. IEEE Micro, 23(6):108-116, 2003.
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• Milo M. K. Martin, Mark D. Hill, and David A. Wood. Token Coherence: Decoupling Performance and Correctness. In 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA, pp. 182-193, IEEE Computer Society, 2003.
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• Milo M. K. Martin, Pacia J. Harper, Daniel J. Sorin, Mark D. Hill, and David A. Wood. Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors. In 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA, pp. 206-217, IEEE Computer Society, 2003.
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• Kevin Skadron, Margaret Martonosi, David I. August, Mark D. Hill, David J. Lilja, and Vijay S. Pai. Challenges in Computer Architecture Evaluation. Computer, 36(8):30-36, 2003.
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• Daniel J. Sorin, Mark D. Hill, and David A. Wood. Dynamic Verification of End-to-End Multiprocessor Invariants. In 2003 International Conference on Dependable Systems and Networks (DSN 2003), 22-25 June 2003, San Francisco, CA, USA, Proceedings, pp. 281-290, IEEE Computer Society, 2003.
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• Min Xu, Rastislav Bodík, and Mark D. Hill. A "Flight Data Recorder" for Enabling Full-System Multiprocessor Deterministic Replay. In 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA, pp. 122-133, IEEE Computer Society, 2003.
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• Anastassia Ailamaki, David J. DeWitt, and Mark D. Hill. Data page layouts for relational databases on deep memory hierarchies. VLDB J., 11(3):198-215, 2002.
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• Brian A. Fields, Rastislav Bodík, and Mark D. Hill. Slack: Maximizing Performance Under Technological Constraints. In 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA, pp. 47-58, IEEE Computer Society, 2002.
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• Milo M. K. Martin, Daniel J. Sorin, Mark D. Hill, and David A. Wood. Bandwidth Adaptive Snooping. In Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), Boston, Massachusettes, USA, February 2-6, 2002, pp. 251-262, IEEE Computer Society, 2002.
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• Carl J. Mauer, Mark D. Hill, and David A. Wood. Full-system timing-first simulation. In Proceedings of the International Conference on Measurements and Modeling of Computer Systems, SIGMETRICS 2002, June 15-19, 2002, Marina Del Rey, California, USA, pp. 108-116, ACM, 2002.
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• Daniel J. Sorin, Manoj Plakal, Anne Condon, Mark D. Hill, Milo M. K. Martin, and David A. Wood. Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol. IEEE Trans. Parallel Distributed Syst., 13(6):556-578, 2002.
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• Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, and David A. Wood. SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery. In 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA, pp. 123-134, IEEE Computer Society, 2002.
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• Anastassia Ailamaki, David J. DeWitt, Mark D. Hill, and Marios Skounakis. Weaving Relations for Cache Performance. In VLDB 2001, Proceedings of 27th International Conference on Very Large Data Bases, September 11-14, 2001, Roma, Italy, pp. 169-180, Morgan Kaufmann, 2001.
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• Jason F. Cantin and Mark D. Hill. Cache performance for selected SPEC CPU2000 benchmarks. SIGARCH Comput. Archit. News, 29(4):13-18, 2001.
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• Milo M. K. Martin, Daniel J. Sorin, Harold W. Cain, Mark D. Hill, and Mikko H. Lipasti. Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing. In Proceedings of the 34th Annual International Symposium on Microarchitecture, Austin, Texas, USA, December 1-5, 2001, pp. 328-337, ACM/IEEE Computer Society, 2001.
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• Eric Schnarr, Mark D. Hill, and James R. Larus. Facile: A Language and Compiler for High-Performance Processor Simulators. In Proceedings of the 2001 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), Snowbird, Utah, USA, June 20-22, 2001, pp. 321-331, ACM, 2001.
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• Trishul M. Chilimbi, Mark D. Hill, and James R. Larus. Making Pointer-Based Data Structures Cache Conscious. Computer, 33(12):67-74, 2000.
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• Mark D. Hill. How computer architecture trends may affect future distributed systems: from infiniBand clusters to inter-processor speculation (abstract). In Proceedings of the Nineteenth Annual ACM Symposium on Principles of Distributed Computing, July 16-19, 2000, Portland, Oregon, USA, pp. 6, ACM, 2000.
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• Milo M. K. Martin, Daniel J. Sorin, Anastassia Ailamaki, Alaa R. Alameldeen, Ross M. Dickson, Carl J. Mauer, Kevin E. Moore, Manoj Plakal, Mark D. Hill, and David A. Wood. Timestamp snooping: an approach for extending SMPs. In ASPLOS-IX Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, MA, USA, November 12-15, 2000, pp. 25-36, ACM Press, 2000.
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• Shubhendu S. Mukherjee, Steven K. Reinhardt, Babak Falsafi, Mike Litzkow, Mark D. Hill, David A. Wood, Steven Huss-Lederman, and James R. Larus. Wisconsin Wind Tunnel II: a fast, portable parallel architecture simulator. IEEE Concurr., 8(4):12-20, 2000.
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• Anastassia Ailamaki, David J. DeWitt, Mark D. Hill, and David A. Wood. DBMSs on a Modern Processor: Where Does Time Go?. In VLDB'99, Proceedings of 25th International Conference on Very Large Data Bases, September 7-10, 1999, Edinburgh, Scotland, UK, pp. 266-277, Morgan Kaufmann, 1999.
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• E. Ender Bilir, Ross M. Dickson, Ying Hu, Manoj Plakal, Daniel J. Sorin, Mark D. Hill, and David A. Wood. Multicast Snooping: A New Coherence Method Using a Multicast Address Network. In Proceedings of the 26th Annual International Symposium on Computer Architecture, ISCA 1999, Atlanta, Georgia, USA, May 2-4, 1999, pp. 294-304, IEEE Computer Society, 1999.
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• Trishul M. Chilimbi, Mark D. Hill, and James R. Larus. Cache-Conscious Structure Layout. In Proceedings of the 1999 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), Atlanta, Georgia, USA, May 1-4, 1999, pp. 1-12, ACM, 1999.
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• Anne Condon, Mark D. Hill, Manoj Plakal, and Daniel J. Sorin. Using Lamport Clocks to Reason about Relaxed Memory Models. In Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, Orlando, FL, USA, January 9-12, 1999, pp. 270-278, IEEE Computer Society, 1999.
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• Mark D. Hill, Anne Condon, Manoj Plakal, and Daniel J. Sorin. A System-Level Specification Framework for I/O Architectures. In Proceedings of the Eleventh Annual ACM Symposium on Parallel Algorithms and Architectures, SPAA '99, Saint-Malo, France, June 27-30, 1999, pp. 138-147, ACM, 1999.
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• Sarita V. Adve and Mark D. Hill. Retrospective: Weak Ordering - A New Definition. In 25 Years of the International Symposia on Computer Architecture (Selected Papers), pp. 63-66, ACM, 1998.
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• Sarita V. Adve and Mark D. Hill. Weak Ordering - A New Definition. In 25 Years of the International Symposia on Computer Architecture (Selected Papers), pp. 363-375, ACM, 1998.
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• Andrew A. Chien, Mark D. Hill, and Shubhendu S. Mukherjee. Design Challenges for High-Performance Network Interfaces - Guest Editors' Introduction. Computer, 31(11):42-44, 1998.
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• Mark D. Hill. Multiprocessors Should Support Simple Memory-Consistency Models. Computer, 31(8):28-34, 1998.
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• Shubhendu S. Mukherjee and Mark D. Hill. Making Network Interfaces Less Peripheral. Computer, 31(10):70-76, 1998.
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• Shubhendu S. Mukherjee and Mark D. Hill. The Impact of Data Transfer and Buffering Alternatives on Network Interface Design. In Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Las Vegas, Nevada, USA, January 31 - February 4, 1998, pp. 207-218, IEEE Computer Society, 1998.
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• Shubhendu S. Mukherjee and Mark D. Hill. Using Prediction to Accelerate Coherence Protocols. In Proceedings of the 25th Annual International Symposium on Computer Architecture, ISCA 1998, Barcelona, Spain, June 27 - July 1, 1998, pp. 179-190, IEEE Computer Society, 1998.
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• Manoj Plakal, Daniel J. Sorin, Anne Condon, and Mark D. Hill. Lamport Clocks: Verifying a Directory Cache-Coherence Protocol. In Proceedings of the Tenth Annual ACM Symposium on Parallel Algorithms and Architectures, SPAA '98, Puerto Vallarta, Mexico, June 28 - July 2, 1998, pp. 67-76, ACM, 1998.
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• Ioannis Schoinas, Babak Falsafi, Mark D. Hill, James R. Larus, and David A. Wood. Sirocco: Cost-Effective Fine-Grain Distributed Shared Memory. In Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, Paris, France, October 12-18, 1998, pp. 40, IEEE Computer Society, 1998.
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• Ioannis Schoinas and Mark D. Hill. Address Translation Mechanisms In Network Interfaces. In Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Las Vegas, Nevada, USA, January 31 - February 4, 1998, pp. 219-230, IEEE Computer Society, 1998.
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• Yuanyuan Zhou, Liviu Iftode, Jaswinder Pal Singh, Kai Li, Brian R. Toonen, Ioannis Schoinas, Mark D. Hill, and David A. Wood. Relaxed Consistency and Coherence Granularity in DSM Systems: A Performance Evaluation. In Proceedings of the Sixth ACM SIGPLAN Symposium on Principles \& Practice of Parallel Programming (PPOPP), Las Vegas, Nevada, USA, June 18-21, 1997, pp. 193-205, ACM, 1997.
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• Sashikanth Chandrasekaran and Mark D. Hill. Optimistic Simulation of Parallel Architectures Using Program Executables. In Proceedings of the Tenth Workshop on Parallel and Distributed Simulation, PADS '96, Philadelphia, PA, USA, May 22-24, 1996, pp. 143-150, IEEE Computer Society, 1996.
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• Shubhendu S. Mukherjee, Babak Falsafi, Mark D. Hill, and David A. Wood. Coherent Network Interfaces for Fine-Grain Communication. In Proceedings of the 23rd Annual International Symposium on Computer Architecture, Philadelphia, PA, USA, May 22-24, 1996, pp. 247-258, ACM, 1996.
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• David A. Wood, Mark D. Hill, and James R. Larus. The Tempest approach to distributed shared memory. In 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 63-64, IEEE Computer Society, 1996.
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• Mark D. Hill, James R. Larus, and David A. Wood. Tempest: A Substrate for Portable Parallel Programs. In COMPCON '95: Technologies for the Information Superhighway, Digest of Papers, San Francisco, California, USA, March 5-9, 1995, pp. 327-332, IEEE Computer Society, 1995.
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• Ted G. Lewis, Dave Power, Bertrand Meyer, Jack Grimes, Mike Potel, Ronald J. Vetter, Phillip A. Laplante, Wolfgang Pree, Gustav Pomberger, Mark D. Hill, James R. Larus, David A. Wood, Hesham El-Rewini, and Bruce W. Weide. Where Is Software Headed? A Virtual Roundtable. Computer, 28(8):20-32, 1995.
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• Shubhendu S. Mukherjee, Shamik D. Sharma, Mark D. Hill, James R. Larus, Anne Rogers, and Joel H. Saltz. Efficient Support for Irregular Applications on Distributed-Memory Machines. In Proceedings of the Fifth ACM SIGPLAN Symposium on Principles \& Practice of Parallel Programming (PPOPP), Santa Barbara, California, USA, July 19-21, 1995, pp. 68-79, ACM, 1995.
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• Madhusudhan Talluri, Mark D. Hill, and Yousef Y. A. Khalidi. A New Page Table for 64-bit Address Spaces. In Proceedings of the Fifteenth ACM Symposium on Operating System Principles, SOSP 1995, Copper Mountain Resort, Colorado, USA, December 3-6, 1995, pp. 184-200, ACM, 1995.
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• David A. Wood and Mark D. Hill. Cost-Effective Parallel Computing. Computer, 28(2):69-72, 1995.
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• Babak Falsafi, Alvin R. Lebeck, Steven K. Reinhardt, Ioannis Schoinas, Mark D. Hill, James R. Larus, Anne Rogers, and David A. Wood. Application-specific protocols for user-level shared memory. In Proceedings Supercomputing '94, Washington, DC, USA, November 14-18, 1994, pp. 380-389, IEEE Computer Society, 1994.
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• Mark D. Hill, James R. Larus, and David A. Wood. The Wisconsin Wind Tunnel project: an annotated bibliography. SIGARCH Comput. Archit. News, 22(5):19-26, 1994.
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• Richard E. Kessler, Mark D. Hill, and David A. Wood. A Comparison of Trace-Sampling Techniques for Multi-Megabyte Caches. IEEE Trans. Computers, 43(6):664-675, 1994.
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• Shubhendu S. Mukherjee and Mark D. Hill. An evaluation of directory protocols for medium-scale shared-memory multiprocessors. In Proceedings of the 8th international conference on Supercomputing, ICS 1994, Manchester, UK, July 11-15, 1994, pp. 64-74, ACM, 1994.
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• Madhusudhan Talluri and Mark D. Hill. Surpassing the TLB Performance of Superpages with Less Operating System Support. In ASPLOS-VI Proceedings - Sixth International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, USA, October 4-7, 1994, pp. 171-182, ACM Press, 1994.
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• Sarita V. Adve and Mark D. Hill. A Unified Formalization of Four Shared-Memory Models. IEEE Trans. Parallel Distributed Syst., 4(6):613-624, 1993.
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• Jeffrey D. Gee, Mark D. Hill, Dionisios N. Pnevmatikatos, and Alan Jay Smith. Cache performance of the SPEC92 benchmark suite. IEEE Micro, 13(4):17-27, 1993.
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• Mark D. Hill, James R. Larus, Alvin R. Lebeck, Madhusudhan Talluri, and David A. Wood. Wisconsin Architectural Research Tool Set. SIGARCH Comput. Archit. News, 21(4):8-10, 1993.
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• Mark D. Hill, James R. Larus, Steven K. Reinhardt, and David A. Wood. Cooperative Shared Memory: Software and Hardware Support for Scalable Multiprocesors. ACM Trans. Comput. Syst., 11(4):300-318, 1993.
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• Andreas Farid Pour and Mark D. Hill. Performance Implications of Tolerating Cache Faults. IEEE Trans. Computers, 42(3):257-267, 1993.
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• Steven K. Reinhardt, Mark D. Hill, James R. Larus, Alvin R. Lebeck, James C. Lewis, and David A. Wood. The Wisconsin Wind Tunnel: Virtual Prototyping of Parallel Computers. In Proceedings of the 1993 ACM SIGMETRICS conference on Measurement and modeling of computer systems, Santa Clara, California, USA, May 10-14, 1993, pp. 48-60, ACM, 1993.
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• David A. Wood, Satish Chandra, Babak Falsafi, Mark D. Hill, James R. Larus, Alvin R. Lebeck, James C. Lewis, Shubhendu S. Mukherjee, Subbarao Palacharla, and Steven K. Reinhardt. Mechanisms for Cooperative Shared Memory. In Proceedings of the 20th Annual International Symposium on Computer Architecture, San Diego, CA, USA, May 1993, pp. 156-167, ACM, 1993.
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• Kourosh Gharachorloo, Sarita V. Adve, Anoop Gupta, John L. Hennessy, and Mark D. Hill. Programming for Different Memory Consistency Models. J. Parallel Distributed Comput., 15(4):399-407, 1992.
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• Mark D. Hill, James R. Larus, Steven K. Reinhardt, and David A. Wood. Cooperative Shared Memory: Software and Hardware Support for Scalable Multiprocesors. In ASPLOS-V Proceedings - Fifth International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, USA, October 12-15, 1992, pp. 262-273, ACM Press, 1992.
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• Richard E. Kessler and Mark D. Hill. Page Placement Algorithms for Large Real-Indexed Caches. ACM Trans. Comput. Syst., 10(4):338-359, 1992.
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• Madhusudhan Talluri, Shing I. Kong, Mark D. Hill, and David A. Patterson. Tradeoffs in Supporting Two Page Sizes. In Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, Australia, May 1992, pp. 415-424, ACM, 1992.
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• Sarita V. Adve, Mark D. Hill, Barton P. Miller, and Robert H. B. Netzer. Detecting Data Races on Weak Memory Systems. In Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, Canada, May, 27-30 1991, pp. 234-243, ACM, 1991.
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• Sarita V. Adve, Vikram S. Adve, Mark D. Hill, and Mary K. Vernon. Comparison of Hardware and Software Cache Coherence Schemes. In Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, Canada, May, 27-30 1991, pp. 298-308, ACM, 1991.
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• Yul H. Kim, Mark D. Hill, and David A. Wood. Implementing Stack Simulation for Highly-Associative Memories. In Proceedings of the 1991 ACM SIGMETRICS conference on Measurement and modeling of computer systems, San Diego, California, USA, May 21-24, 1991, pp. 212-213, ACM, 1991.
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• David A. Wood, Mark D. Hill, and Richard E. Kessler. A Model for Estimating Trace-Sample Miss Ratios. In Proceedings of the 1991 ACM SIGMETRICS conference on Measurement and modeling of computer systems, San Diego, California, USA, May 21-24, 1991, pp. 79-89, ACM, 1991.
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• Sarita V. Adve and Mark D. Hill. Implementing Sequential Consistency in Cache-Based Systems. In Proceedings of the 1990 International Conference on Parallel Processing, Urbana-Champaign, IL, USA, August 1990. Volume 1: Architecture, pp. 47-50, Pennsylvania State University Press, 1990.
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• Sarita V. Adve and Mark D. Hill. Weak Ordering - A New Definition. In Proceedings of the 17th Annual International Symposium on Computer Architecture, Seattle, WA, USA, June 1990, pp. 2-14, ACM, 1990.
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• Mark D. Hill and James R. Larus. Cache Considerations for Multiprocessor Programmers. Commun. ACM, 33(8):97-102, 1990.
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• Mark D. Hill. What is scalability?. SIGARCH Comput. Archit. News, 18(4):18-21, 1990.
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• Dionisios N. Pnevmatikatos and Mark D. Hill. Cache performance of the integer SPEC benchmarks on a RISC. SIGARCH Comput. Archit. News, 18(2):53-68, 1990.
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• Mark D. Hill and Alan Jay Smith. Evaluating Associativity in CPU Caches. IEEE Trans. Computers, 38(12):1612-1630, 1989.
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• Richard E. Kessler, Richard Jooss, Alvin R. Lebeck, and Mark D. Hill. Inexpensive Implementations of Set-Associativity. In Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, Israel, June 1989, pp. 131-139, ACM, 1989.
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• Mark D. Hill. A Case for Direct-Mapped Caches. Computer, 21(12):25-40, 1988.
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• David A. Wood, Susan J. Eggers, Garth A. Gibson, Mark D. Hill, Joan M. Pendleton, Scott A. Ritchie, George S. Taylor, Randy H. Katz, and David A. Patterson. An In-Cache Address Translation Mechanism. In Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, pp. 358-365, IEEE Computer Society, 1986.
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• Mark D. Hill and Alan Jay Smith. Experimental Evaluation of On-Chip Microprocessor Cache Memories. In Proceedings of the 11th Annual Symposium on Computer Architecture, Ann Arbor, USA, June 1984, pp. 158-166, ACM, 1984.
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• David A. Patterson, Phil Garrison, Mark D. Hill, Dimitris Lioupis, Chris Nyberg, Tim Sippel, and Korbin S. Van Dyke. Architecture of a VLSI Instruction Cache for a RISC. In Proceedings of the 10th Annual Symposium on Computer Architecture, 1983, pp. 108-116, ACM, 1983.
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Lipasti

• Sooraj Puthoor and Mikko H. Lipasti. Systems-on-Chip with Strong Ordering. ACM Trans. Archit. Code Optim., 18(1):15:1-15:27, 2021.
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• Gokul Subramanian Ravi, Ramon Bertran, Pradip Bose, and Mikko H. Lipasti. MicroGrad: A Centralized Framework for Workload Cloning and Stress Testing. In IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2021, Stony Brook, NY, USA, March 28-30, 2021, pp. 70-72, IEEE, 2021.
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• Kyle Daruwalla, Heng Zhuo, Rohit Shukla, and Mikko H. Lipasti. BitSAD v2: Compiler Optimization and Analysis for Bitstream Computing. ACM Trans. Archit. Code Optim., 16(4):43:1-43:25, 2020.
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• Ravi S. Raju and Mikko H. Lipasti. BlurNet: Defense by Filtering the Feature Maps. In 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, DSN Workshops 2020, Valencia, Spain, June 29 - July 2, 2020, pp. 38-46, IEEE, 2020.
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• Gokul Subramanian Ravi, Joshua San Miguel, and Mikko H. Lipasti. SHASTA: Synergic HW-SW Architecture for Spatio-temporal Approximation. ACM Trans. Archit. Code Optim., 17(4):25:1-25:26, 2020.
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• Gokul Subramanian Ravi, Ramon Bertran, Pradip Bose, and Mikko H. Lipasti. MicroGrad: A Centralized Framework for Workload Cloning and Stress Testing. CoRR, abs/2009.04622, 2020.
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• David J. Schlais, Heng Zhuo, and Mikko H. Lipasti. Modeling Architectural Support for Tightly-Coupled Accelerators. In IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2020, Boston, MA, USA, August 23-25, 2020, pp. 253-262, IEEE, 2020.
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• Rahul Singh, Gokul Subramanian Ravi, Mikko H. Lipasti, and Joshua San Miguel. Value Locality Based Approximation With ODIN. IEEE Comput. Archit. Lett., 19(2):88-91, 2020.
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• Kyle Daruwalla, Heng Zhuo, Carly Schulz, and Mikko H. Lipasti. BitBench: a benchmark for bitstream computing. In Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems, LCTES 2019, Phoenix, AZ, USA, June 23-23, 2019, pp. 177-187, ACM, 2019.
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• Ravi S. Raju and Mikko H. Lipasti. BlurNet: Defense by Filtering the Feature Maps. CoRR, abs/1908.02256, 2019.
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• Gokul Subramanian Ravi and Mikko H. Lipasti. Recycling Data Slack in Out-of-Order Cores. In 25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019, Washington, DC, USA, February 16-20, 2019, pp. 545-557, IEEE, 2019.
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• Di Wu, Tianen Chen, Chienfu Chen, Oghenefego Ahia, Joshua San Miguel, Mikko H. Lipasti, and Younghyun Kim. SECO: A Scalable Accuracy Approximate Exponential Function Via Cross-Layer Optimization. In 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019, Lausanne, Switzerland, July 29-31, 2019, pp. 1-6, IEEE, 2019.
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• Sooraj Puthoor and Mikko H. Lipasti. Compiler assisted coalescing. In Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, PACT 2018, Limassol, Cyprus, November 01-04, 2018, pp. 11:1-11:11, ACM, 2018.
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• Gokul Subramanian Ravi and Mikko H. Lipasti. Aggressive Slack Recycling via Transparent Pipelines. In Proceedings of the International Symposium on Low Power Electronics and Design, ISLPED 2018, Seattle, WA, USA, July 23-25, 2018, pp. 15:1-15:6, ACM, 2018.
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• Dibakar Gope, David J. Schlais, and Mikko H. Lipasti. Architectural Support for Server-Side PHP Processing. In Proceedings of the 44th Annual International Symposium on Computer Architecture, ISCA 2017, Toronto, ON, Canada, June 24-28, 2017, pp. 507-520, ACM, 2017.
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• Michael Mishkin, Nam Sung Kim, and Mikko H. Lipasti. Temporal codes in on-chip interconnects. In 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2017, Taipei, Taiwan, July 24-26, 2017, pp. 1-6, IEEE, 2017.
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• Vignyan Reddy Kothinti Naresh, Dibakar Gope, and Mikko H. Lipasti. The CURE: Cluster Communication Using Registers. ACM Trans. Embed. Comput. Syst., 16(5s):124:1-124:19, 2017.
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• Gokul Subramanian Ravi and Mikko H. Lipasti. Timing Speculation in Multi-Cycle Data Paths. IEEE Comput. Archit. Lett., 16(1):84-87, 2017.
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• Gokul Subramanian Ravi and Mikko H. Lipasti. CHARSTAR: Clock Hierarchy Aware Resource Scaling in Tiled ARchitectures. In Proceedings of the 44th Annual International Symposium on Computer Architecture, ISCA 2017, Toronto, ON, Canada, June 24-28, 2017, pp. 147-160, ACM, 2017.
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• Rohit Shukla, Erik Jorgensen, and Mikko H. Lipasti. Evaluating hopfield-network-based linear solvers for hardware constrained neural substrates. In 2017 International Joint Conference on Neural Networks, IJCNN 2017, Anchorage, AK, USA, May 14-19, 2017, pp. 3938-3945, IEEE, 2017.
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• Dibakar Gope and Mikko H. Lipasti. Hash Map Inlining. In Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, PACT 2016, Haifa, Israel, September 11-15, 2016, pp. 235-246, ACM, 2016.
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• David J. Schlais and Mikko H. Lipasti. BADGR: A practical GHR implementation for TAGE branch predictors. In 34th IEEE International Conference on Computer Design, ICCD 2016, Scottsdale, AZ, USA, October 2-5, 2016, pp. 536-543, IEEE Computer Society, 2016.
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• Sean Franey and Mikko H. Lipasti. Tag tables. In 21st IEEE International Symposium on High Performance Computer Architecture, HPCA 2015, Burlingame, CA, USA, February 7-11, 2015, pp. 514-525, IEEE Computer Society, 2015.
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• David J. Palframan, Nam Sung Kim, and Mikko H. Lipasti. iPatch: Intelligent fault patching to improve energy efficiency. In 21st IEEE International Symposium on High Performance Computer Architecture, HPCA 2015, Burlingame, CA, USA, February 7-11, 2015, pp. 428-438, IEEE Computer Society, 2015.
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• David J. Palframan, Nam Sung Kim, and Mikko H. Lipasti. COP: to compress and protect main memory. In Proceedings of the 42nd Annual International Symposium on Computer Architecture, Portland, OR, USA, June 13-17, 2015, pp. 682-693, ACM, 2015.
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• Rohit Shukla and Mikko H. Lipasti. A self-learning map-seeking circuit for visual object recognition. In 2015 International Joint Conference on Neural Networks, IJCNN 2015, Killarney, Ireland, July 12-17, 2015, pp. 1-8, IEEE, 2015.
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• Amir Yazdanbakhsh, David J. Palframan, Azadeh Davoodi, Nam Sung Kim, and Mikko H. Lipasti. Online and Operand-Aware Detection of Failures Utilizing False Alarm Vectors. In Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20 - 22, 2015, pp. 149-154, ACM, 2015.
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• Zhong Zheng, Zhiying Wang, and Mikko H. Lipasti. Adaptive Cache and Concurrency Allocation on GPGPUs. IEEE Comput. Archit. Lett., 14(2):90-93, 2015.
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• Dibakar Gope and Mikko H. Lipasti. Atomic SC for simple in-order processors. In 20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014, Orlando, FL, USA, February 15-19, 2014, pp. 404-415, IEEE Computer Society, 2014.
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• Dibakar Gope and Mikko H. Lipasti. Bias-Free Branch Predictor. In 47th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2014, Cambridge, United Kingdom, December 13-17, 2014, pp. 521-532, IEEE Computer Society, 2014.
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• Mitchell Hayenga, Vignyan Reddy Kothinti Naresh, and Mikko H. Lipasti. Revolver: Processor architecture for power efficient loop execution. In 20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014, Orlando, FL, USA, February 15-19, 2014, pp. 591-602, IEEE Computer Society, 2014.
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• David J. Palframan, Nam Sung Kim, and Mikko H. Lipasti. Precision-aware soft error protection for GPUs. In 20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014, Orlando, FL, USA, February 15-19, 2014, pp. 49-59, IEEE Computer Society, 2014.
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• Zhong Zheng, Zhiying Wang, and Mikko H. Lipasti. Tag check elision. In International Symposium on Low Power Electronics and Design, ISLPED'14, La Jolla, CA, USA - August 11 - 13, 2014, pp. 351-356, ACM, 2014.
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• Sean Franey and Mikko H. Lipasti. Accelerating atomic operations on GPGPUs. In 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), Tempe, AZ, USA, April 21-24, 2013, pp. 1-8, IEEE, 2013.
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• Mushfique Junayed Khurshid and Mikko H. Lipasti. Data compression for thermal mitigation in the Hybrid Memory Cube. In 2013 IEEE 31st International Conference on Computer Design, ICCD 2013, Asheville, NC, USA, October 6-9, 2013, pp. 185-192, IEEE Computer Society, 2013.
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• Andrew Nere, Sean Franey, Atif Hashmi, and Mikko H. Lipasti. Simulating cortical networks on heterogeneous multi-GPU systems. J. Parallel Distributed Comput., 73(7):953-971, 2013.
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• Andrew Nere, Atif Hashmi, Mikko H. Lipasti, and Giulio Tononi. Bridging the semantic gap: Emulating biological neuronal behaviors with simple digital neurons. In 19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013, Shenzhen, China, February 23-27, 2013, pp. 472-483, IEEE Computer Society, 2013.
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• David J. Palframan, Nam Sung Kim, and Mikko H. Lipasti. Resilient High-Performance Processors with Spare RIBs. IEEE Micro, 33(4):26-34, 2013.
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• Vignyan Reddy, Syed Zohaib Gilani, Erika Gunadi, Nam Sung Kim, Michael J. Schulte, and Mikko H. Lipasti. REEL: Reducing effective execution latency of floating point operations. In International Symposium on Low Power Electronics and Design (ISLPED), Beijing, China, September 4-6, 2013, pp. 187-192, IEEE, 2013.
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• Arslan Zulfiqar, Pranay Koka, Herb Schwetman, Mikko H. Lipasti, Xuezhe Zheng, and Ashok V. Krishnamoorthy. Wavelength stealing: an opportunistic approach to channel sharing in multi-chip photonic interconnects. In The 46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-46, Davis, CA, USA, December 7-11, 2013, pp. 222-233, ACM, 2013.
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• Harold W. Cain and Mikko H. Lipasti. Edge chasing delayed consistency: pushing the limits of weak memory models. In Proceedings of the 2012 ACM workshop on Relaxing synchronization for multicore and manycore scalability, RACES@SPLASH 2012, Tucson, Arizona, USA, October 21, 2012, pp. 15-24, ACM, 2012.
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• Tianshi Chen, Yunji Chen, Marc Duranton, Qi Guo, Atif Hashmi, Mikko H. Lipasti, Andrew Nere, Shi Qiu, Michèle Sebag, and Olivier Temam. BenchNN: On the broad potential application scope of hardware neural network accelerators. In Proceedings of the 2012 IEEE International Symposium on Workload Characterization, IISWC 2012, La Jolla, CA, USA, November 4-6, 2012, pp. 36-45, IEEE Computer Society, 2012.
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• David J. Palframan, Nam Sung Kim, and Mikko H. Lipasti. Mitigating random variation with spare RIBs: Redundant intermediate bitslices. In IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2012, Boston, MA, USA, June 25-28, 2012, pp. 1-11, IEEE Computer Society, 2012.
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• Erika Gunadi and Mikko H. Lipasti. CRIB: consolidated rename, issue, and bypass. In 38th International Symposium on Computer Architecture (ISCA 2011), June 4-8, 2011, San Jose, CA, USA, pp. 23-32, ACM, 2011.
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• Atif Hashmi, Andrew Nere, James Jamal Thomas, and Mikko H. Lipasti. A case for neuromorphic ISAs. In Proceedings of the 16th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2011, Newport Beach, CA, USA, March 5-11, 2011, pp. 145-158, ACM, 2011.
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• Atif Hashmi, Hugues Berry, Olivier Temam, and Mikko H. Lipasti. Automatic abstraction and fault tolerance in cortical microachitectures. In 38th International Symposium on Computer Architecture (ISCA 2011), June 4-8, 2011, San Jose, CA, USA, pp. 1-10, ACM, 2011.
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• Mitchell Hayenga and Mikko H. Lipasti. The NoX router. In 44rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2011, Porto Alegre, Brazil, December 3-7, 2011, pp. 36-46, ACM, 2011.
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• Natalie D. Enright Jerger and Mikko H. Lipasti. Systems for Very Large-Scale Computing. IEEE Micro, 31(3):4-7, 2011.
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• Vignyan Reddy Kothinti Naresh, David J. Palframan, and Mikko H. Lipasti. CRAM: coded registers for amplified multiporting. In 44rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2011, Porto Alegre, Brazil, December 3-7, 2011, pp. 196-205, ACM, 2011.
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• Andrew Nere, Atif Hashmi, and Mikko H. Lipasti. Profiling Heterogeneous Multi-GPU Systems to Accelerate Cortically Inspired Learning Algorithms. In 25th IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2011, Anchorage, Alaska, USA, 16-20 May, 2011 - Conference Proceedings, pp. 906-920, IEEE, 2011.
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• David J. Palframan, Nam Sung Kim, and Mikko H. Lipasti. Time redundant parity for low-cost transient error detection. In Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011, pp. 52-57, IEEE, 2011.
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• Guangyu Shi, Min Li, and Mikko H. Lipasti. Accelerating search and recognition workloads with SSE 4.2 string and text processing instructions. In IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2011, 10-12 April, 2011, Austin, TX, USA, pp. 145-153, IEEE Computer Society, 2011.
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• Dana Vantrease, Mikko H. Lipasti, and Nathan L. Binkert. Atomic Coherence: Leveraging nanophotonics to build race-free cache coherence protocols. In 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), February 12-16 2011, San Antonio, Texas, USA, pp. 132-143, IEEE Computer Society, 2011.
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• Erika Gunadi, Abhishek A. Sinkar, Nam Sung Kim, and Mikko H. Lipasti. Combating Aging with the Colt Duty Cycle Equalizer. In 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2010, 4-8 December 2010, Atlanta, Georgia, USA, pp. 103-114, IEEE Computer Society, 2010.
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• Atif Hashmi and Mikko H. Lipasti. Discovering Cortical Algorithms. In ICFC-ICNC 2010 - Proceedings of the International Conference on Fuzzy Computation and International Conference on Neural Computation, [parts of the International Joint Conference on Computational Intelligence IJCCI 2010], Valencia, Spain, October 24-26, 2010, pp. 196-204, SciTePress, 2010.
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• Atif Hashmi and Mikko H. Lipasti. A Cortically Inspired Learning Model. In Computational Intelligence - Revised and Selected Papers of the International Joint Conference, IJCCI 2010, Valencia, Spain, October 2010, pp. 373-388, Springer, 2010.
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• Andrew Nere and Mikko H. Lipasti. Cortical architectures on a GPGPU. In Proceedings of 3rd Workshop on General Purpose Processing on Graphics Processing Units, GPGPU 2010, Pittsburgh, Pennsylvania, USA, March 14, 2010, pp. 12-18, ACM, 2010.
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• Dennis Abts, Natalie D. Enright Jerger, John Kim, Dan Gibson, and Mikko H. Lipasti. Achieving predictable performance through better memory controller placement in many-core CMPs. In 36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA, pp. 451-461, ACM, 2009.
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• Atif Hashmi and Mikko H. Lipasti. Cortical columns: Building blocks for intelligent systems. In 2009 IEEE Symposium on Computational Intelligence for Multimedia Signal and Vision Processing, CIMSVP 2009, Nashville, TN, USA, March 31 - April 1, 2009, pp. 21-28, IEEE, 2009.
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• Mitchell Hayenga, Natalie D. Enright Jerger, and Mikko H. Lipasti. SCARAB: a single cycle adaptive routing and bufferless network. In 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 244-254, ACM, 2009.
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• Dana Vantrease, Nathan L. Binkert, Robert Schreiber, and Mikko H. Lipasti. Light speed arbitration and flow control for nanophotonic interconnects. In 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 304-315, ACM, 2009.
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• Nidhi Aggarwal, Jason F. Cantin, Mikko H. Lipasti, and James E. Smith. Power-Efficient DRAM Speculation. In 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 16-20 February 2008, Salt Lake City, UT, USA, pp. 317-328, IEEE Computer Society, 2008.
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• Gordon B. Bell and Mikko H. Lipasti. Skewed redundancy. In 17th International Conference on Parallel Architectures and Compilation Techniques, PACT 2008, Toronto, Ontario, Canada, October 25-29, 2008, pp. 62-71, ACM, 2008.
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• Atif Hashmi and Mikko H. Lipasti. Accelerating search and recognition with a TCAM functional unit. In 26th International Conference on Computer Design, ICCD 2008, 12-15 October 2008, Lake Tahoe, CA, USA, Proceedings, pp. 81-86, IEEE Computer Society, 2008.
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• Eric L. Hill, Mikko H. Lipasti, and Kewal K. Saluja. An accurate flip-flop selection technique for reducing logic SER. In The 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2008, June 24-27, 2008, Anchorage, Alaska, USA, Proceedings, pp. 128-136, IEEE Computer Society, 2008.
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• Natalie D. Enright Jerger, Li-Shiuan Peh, and Mikko H. Lipasti. Virtual Circuit Tree Multicasting: A Case for On-Chip Hardware Multicast Support. In 35th International Symposium on Computer Architecture (ISCA 2008), June 21-25, 2008, Beijing, China, pp. 229-240, IEEE Computer Society, 2008.
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• Natalie D. Enright Jerger, Li-Shiuan Peh, and Mikko H. Lipasti. Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherence. In 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy, pp. 35-46, IEEE Computer Society, 2008.
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• Natalie D. Enright Jerger, Li-Shiuan Peh, and Mikko H. Lipasti. Circuit-Switched Coherence. In Second International Symposium on Networks-on-Chips, NOCS 2008, 5-6 April 2008, Newcastle University, UK. Proceedings, pp. 193-202, IEEE Computer Society, 2008.
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• Erika Gunadi and Mikko H. Lipasti. Narrow Width Dynamic Scheduling. J. Instr. Level Parallelism, 9, 2007.
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• Erika Gunadi and Mikko H. Lipasti. A position-insensitive finished store buffer. In 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 105-112, IEEE, 2007.
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• Erika Gunadi and Mikko H. Lipasti. Power-aware operand delivery. In Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007, pp. 375-378, ACM, 2007.
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• Eric L. Hill and Mikko H. Lipasti. Transparent mode flip-flops for collapsible pipelines. In 25th International Conference on Computer Design, ICCD 2007, 7-10 October 2007, Lake Tahoe, CA, USA, Proceedings, pp. 553-560, IEEE, 2007.
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• Natalie D. Enright Jerger, Mikko H. Lipasti, and Li-Shiuan Peh. Circuit-Switched Coherence. IEEE Comput. Archit. Lett., 6(1):5-8, 2007.
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• Natalie D. Enright Jerger, Dana Vantrease, and Mikko H. Lipasti. An Evaluation of Server Consolidation Workloads for Multi-Core Designs. In IEEE 10th International Symposium on Workload Characterization, IISWC 2007, Boston, MA, USA, 27-29 September, 2007, pp. 47-56, IEEE Computer Society, 2007.
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• Lixin Su and Mikko H. Lipasti. Speculative optimization using hardware-monitored guarded regions for java virtual machines. In Proceedings of the 3rd International Conference on Virtual Execution Environments, VEE 2007, San Diego, California, USA, June 13-15, 2007, pp. 22-32, ACM, 2007.
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• Jason F. Cantin, James E. Smith, Mikko H. Lipasti, Andreas Moshovos, and Babak Falsafi. Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays. IEEE Micro, 26(1):70-79, 2006.
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• Jason F. Cantin, Mikko H. Lipasti, and James E. Smith. Stealth prefetching. In Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2006, San Jose, CA, USA, October 21-25, 2006, pp. 274-282, ACM, 2006.
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• Eric L. Hill and Mikko H. Lipasti. Stall cycle redistribution in a transparent fetch pipeline. In Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 31-36, ACM, 2006.
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• Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, and James E. Smith. An approach for implementing efficient superscalar CISC processors. In 12th International Symposium on High-Performance Computer Architecture, HPCA-12 2006, Austin, Texas, USA, February 11-15, 2006, pp. 41-52, IEEE Computer Society, 2006.
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• Natalie D. Enright Jerger, Eric L. Hill, and Mikko H. Lipasti. Friendly fire: understanding the effects of multiprocessor prefetches. In 2006 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2006, March 19-21, 2006, Austin, Texas, USA, Proceedings, pp. 177-188, IEEE Computer Society, 2006.
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• Lixin Su and Mikko H. Lipasti. Dynamic Class Hierarchy Mutation. In Fourth IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2006), 26-29 March 2006, New York, New York, USA, pp. 98-110, IEEE Computer Society, 2006.
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• Eric F. Weglarz, Kewal K. Saluja, and Mikko H. Lipasti. Energy Estimation of the Memory Subsystem in Multiprocessor Systems. J. Low Power Electron., 2(3):325-332, 2006.
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• Jason F. Cantin, Mikko H. Lipasti, and James E. Smith. The Complexity of Verifying Memory Coherence and Consistency. IEEE Trans. Parallel Distributed Syst., 16(7):663-671, 2005.
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• Jason F. Cantin, Mikko H. Lipasti, and James E. Smith. Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking. In 32st International Symposium on Computer Architecture (ISCA 2005), 4-8 June 2005, Madison, Wisconsin, USA, pp. 246-257, IEEE Computer Society, 2005.
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• Kevin M. Lepak and Mikko H. Lipasti. Reaping the Benefit of Temporal Silence to Improve Communication Performance. In IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2005, March 20-22, 2005, Austin, Texas, USA, Proceedings, pp. 258-268, IEEE Computer Society, 2005.
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• Gordon B. Bell and Mikko H. Lipasti. Deconstructing commit. In 2004 IEEE International Symposium on Performance Analysis of Systems and Software, March 10-12, 2004, Austin, Texas, USA, Proceedings, pp. 68-77, IEEE Computer Society, 2004.
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• Harold W. Cain, Mikko H. Lipasti, and Ravi Nair. Constraint Graph Analysis of Multithreaded Programs. J. Instr. Level Parallelism, 6, 2004.
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• Harold W. Cain and Mikko H. Lipasti. Memory Ordering: A Value-Based Approach. IEEE Micro, 24(6):110-117, 2004.
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• Harold W. Cain and Mikko H. Lipasti. Memory Ordering: A Value-Based Approach. In 31st International Symposium on Computer Architecture (ISCA 2004), 19-23 June 2004, Munich, Germany, pp. 90-101, IEEE Computer Society, 2004.
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• Ilhyun Kim and Mikko H. Lipasti. Understanding Scheduling Replay Schemes. In 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 14-18 February 2004, Madrid, Spain, pp. 198-209, IEEE Computer Society, 2004.
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• Mikko H. Lipasti, Brian R. Mestan, and Erika Gunadi. Physical Register Inlining. In 31st International Symposium on Computer Architecture (ISCA 2004), 19-23 June 2004, Munich, Germany, pp. 325-337, IEEE Computer Society, 2004.
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• Harold W. Cain, Mikko H. Lipasti, and Ravi Nair. Constraint Graph Analysis of Multithreaded Programs. In 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September - 1 October 2003, New Orleans, LA, USA, pp. 4-14, IEEE Computer Society, 2003.
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• Jason F. Cantin, Mikko H. Lipasti, and James E. Smith. The complexity of verifying memory coherence. In SPAA 2003: Proceedings of the Fifteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures, June 7-9, 2003, San Diego, California, USA (part of FCRC 2003), pp. 254-255, ACM, 2003.
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• Ilhyun Kim and Mikko H. Lipasti. Half-Price Architecture. In 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA, pp. 28-38, IEEE Computer Society, 2003.
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• Ilhyun Kim and Mikko H. Lipasti. Macro-op Scheduling: Relaxing Scheduling Loop Constraints. In Proceedings of the 36th Annual International Symposium on Microarchitecture, San Diego, CA, USA, December 3-5, 2003, pp. 277-290, IEEE Computer Society, 2003.
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• Kevin M. Lepak, Harold W. Cain, and Mikko H. Lipasti. Redeeming IPC as a Performance Metric for Multithreaded Programs. In 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September - 1 October 2003, New Orleans, LA, USA, pp. 232-243, IEEE Computer Society, 2003.
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• Brian R. Mestan and Mikko H. Lipasti. Exploiting Partial Operand Knowledge. In 32nd International Conference on Parallel Processing (ICPP 2003), 6-9 October 2003, Kaohsiung, Taiwan, pp. 369-378, IEEE Computer Society, 2003.
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• Harold W. Cain and Mikko H. Lipasti. Verifying sequential consistency using vector clocks. In Proceedings of the Fourteenth Annual ACM Symposium on Parallel Algorithms and Architectures, SPAA 2002, Winnipeg, Manitoba, Canada, August 11-13, 2002, pp. 153-154, ACM, 2002.
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• Ilhyun Kim and Mikko H. Lipasti. Implementing Optimizations at Decode Time. In 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA, pp. 221-232, IEEE Computer Society, 2002.
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• Kevin M. Lepak and Mikko H. Lipasti. Temporally silent stores. In Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), San Jose, California, USA, October 5-9, 2002, pp. 30-41, ACM Press, 2002.
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• Jarrod A. Lewis, Mikko H. Lipasti, and Bryan Black. Avoiding Initialization Misses to the Heap. In 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA, pp. 183-194, IEEE Computer Society, 2002.
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• Eric F. Weglarz, Kewal K. Saluja, and Mikko H. Lipasti. Minimizing Energy Consumption for High-Performance Processing. In Proceedings of the ASPDAC 2002 / VLSI Design 2002, CD-ROM, 7-11 January 2002, Bangalore, India, pp. 199, IEEE Computer Society, 2002.
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• Harold W. Cain, Kevin M. Lepak, and Mikko H. Lipasti. A dynamic binary translation approach to architectural simulation. SIGARCH Comput. Archit. News, 29(1):27-36, 2001.
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• Harold W. Cain, Ravi Rajwar, Morris Marden, and Mikko H. Lipasti. An Architectural Evaluation of Java TPC-W. In Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), Nuevo Leone, Mexico, January 20-24, 2001, pp. 229-240, IEEE Computer Society, 2001.
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• Kevin M. Lepak, Gordon B. Bell, and Mikko H. Lipasti. Silent Stores and Store Value Locality. IEEE Trans. Computers, 50(11):1174-1190, 2001.
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• Milo M. K. Martin, Daniel J. Sorin, Harold W. Cain, Mark D. Hill, and Mikko H. Lipasti. Correctly implementing value prediction in microprocessors that support multithreading or multiprocessing. In Proceedings of the 34th Annual International Symposium on Microarchitecture, Austin, Texas, USA, December 1-5, 2001, pp. 328-337, ACM/IEEE Computer Society, 2001.
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• Gordon B. Bell, Kevin M. Lepak, and Mikko H. Lipasti. Characterization of Silent Stores. In Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques (PACT'00), Philadelphia, Pennsylvania, USA, October 15-19, 2000, pp. 133-144, IEEE Computer Society, 2000.
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• Steven R. Kunkel, Richard J. Eickemeyer, Mikko H. Lipasti, Timothy J. Mullins, Brian O'Krafka, Harold Rosenberg, Steven P. Vanderwiel, Philip L. Vitale, and Larry D. Whitley. A performance methodology for commercial servers. IBM J. Res. Dev., 44(6):851-872, 2000.
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• Kevin M. Lepak and Mikko H. Lipasti. On the value locality of store instructions. In 27th International Symposium on Computer Architecture (ISCA 2000), June 10-14, 2000, Vancouver, BC, Canada, pp. 182-191, IEEE Computer Society, 2000.
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• Kevin M. Lepak and Mikko H. Lipasti. Silent stores for free. In Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 33, Monterey, California, USA, December 10-13, 2000, pp. 22-31, ACM/IEEE Computer Society, 2000.
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• Derek L. Howard and Mikko H. Lipasti. The Effect of Program Optimization on Trace Cache Efficiency. In Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, Newport Beach, California, USA, October 12-16, 1999, pp. 256-261, IEEE Computer Society, 1999.
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• Mikko H. Lipasti and John Paul Shen. Exploiting Value Locality to Exceed the Dataflow Limit. Int. J. Parallel Program., 26(4):505-538, 1998.
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• Mikko H. Lipasti and John Paul Shen. Superspeculative Microarchitecture for Beyond AD 2000. Computer, 30(9):59-66, 1997.
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• Mikko H. Lipasti and John Paul Shen. The Performance Potential of Value and Dependence Prediction. In Euro-Par '97 Parallel Processing, Third International Euro-Par Conference, Passau, Germany, August 26-29, 1997, Proceedings, pp. 1043-1052, Springer, 1997.
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• Bryan Black, Andrew S. Huang, Mikko H. Lipasti, and John Paul Shen. Can Trace-Driven Simulators Accurately Predict Superscalar Performance?. In 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 478-485, IEEE Computer Society, 1996.
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• Mikko H. Lipasti, Christopher B. Wilkerson, and John Paul Shen. Value Locality and Load Value Prediction. In ASPLOS-VII Proceedings - Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, Massachusetts, USA, October 1-5, 1996, pp. 138-147, ACM Press, 1996.
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• Mikko H. Lipasti and John Paul Shen. Exceeding the Dataflow Limit via Value Prediction. In Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 226-237, ACM/IEEE Computer Society, 1996.
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• Mikko H. Lipasti, William J. Schmidt, Steven R. Kunkel, and Robert R. Roediger. SPAID: software prefetching in pointer- and call-intensive environments. In Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29 - December 1, 1995, pp. 231-236, ACM / IEEE Computer Society, 1995.
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• Trung A. Diep, Mikko H. Lipasti, and John Paul Shen. Architecture-Compatible Code Boosting for Performance Enhancement of the IBM RS/6000. In Proceedings 1993 International Conference on Computer Design: VLSI in Computers \& Processors, ICCD '93, Cambridge, MA, USA, October 3-6, 1993, pp. 86-93, IEEE Computer Society, 1993.
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Miguel

• Hossein Farrokhbakht, Henry Kao, Kamran Hasan, Paul V. Gratz, Tushar Krishna, Joshua San Miguel, and Natalie D. Enright Jerger. Pitstop: Enabling a Virtual Network Free Network-on-Chip. In IEEE International Symposium on High-Performance Computer Architecture, HPCA 2021, Seoul, South Korea, February 27 - March 3, 2021, pp. 682-695, IEEE, 2021.
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• Maedeh Hemmat, Joshua San Miguel, and Azadeh Davoodi. AirNN: A Featherweight Framework for Dynamic Input-Dependent Approximation of CNNs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40(10):2090-2103, 2021.
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• Hsuan Hsiao, Joshua San Miguel, Yuko Hara-Azumi, and Jason Helge Anderson. Zero Correlation Error: A Metric for Finite-Length Bitstream Independence in Stochastic Computing. In ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, Tokyo, Japan, January 18-21, 2021, pp. 260-265, ACM, 2021.
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• Di Wu, Jingjie Li, Ruokai Yin, Hsuan Hsiao, Younghyun Kim, and Joshua San Miguel. uGEMM: Unary Computing for GEMM Applications. IEEE Micro, 41(3):50-56, 2021.
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• Di Wu, Ruokai Yin, and Joshua San Miguel. Normalized Stability: A Cross-Level Design Metric for Early Termination in Stochastic Computing. In ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, Tokyo, Japan, January 18-21, 2021, pp. 254-259, ACM, 2021.
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• Di Wu, Jingjie Li, Setareh Behroozi, Younghyun Kim, and Joshua San Miguel. UNO: Virtualizing and Unifying Nonlinear Operations for Emerging Neural Networks. In IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2021, Boston, MA, USA, July 26-28, 2021, pp. 1-6, IEEE, 2021.
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• Chen Chen, Zirui Tao, and Joshua San Miguel. Bufferless NoCs with Scheduled Deflection Routing. In 14th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2020, Hamburg, Germany, September 24-25, 2020, pp. 1-6, IEEE, 2020.
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• Maedeh Hemmat, Tejas Shah, Yuhua Chen, and Joshua San Miguel. CRANIA: Unlocking Data and Value Reuse in Iterative Neural Network Architectures. In 25th Asia and South Pacific Design Automation Conference, ASP-DAC 2020, Beijing, China, January 13-16, 2020, pp. 295-300, IEEE, 2020.
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• Maedeh Hemmat, Joshua San Miguel, and Azadeh Davoodi. CAP'NN: Class-Aware Personalized Neural Network Inference. In 57th ACM/IEEE Design Automation Conference, DAC 2020, San Francisco, CA, USA, July 20-24, 2020, pp. 1-6, IEEE, 2020.
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• Mayank Parasar, Hossein Farrokhbakht, Natalie D. Enright Jerger, Paul V. Gratz, Tushar Krishna, and Joshua San Miguel. DRAIN: Deadlock Removal for Arbitrary Irregular Networks. In IEEE International Symposium on High Performance Computer Architecture, HPCA 2020, San Diego, CA, USA, February 22-26, 2020, pp. 447-460, IEEE, 2020.
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• Gokul Subramanian Ravi, Joshua San Miguel, and Mikko H. Lipasti. SHASTA: Synergic HW-SW Architecture for Spatio-temporal Approximation. ACM Trans. Archit. Code Optim., 17(4):25:1-25:26, 2020.
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• Rahul Singh, Gokul Subramanian Ravi, Mikko H. Lipasti, and Joshua San Miguel. Value Locality Based Approximation With ODIN. IEEE Comput. Archit. Lett., 19(2):88-91, 2020.
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• Di Wu, Jingjie Li, Ruokai Yin, Hsuan Hsiao, Younghyun Kim, and Joshua San Miguel. UGEMM: Unary Computing Architecture for GEMM Applications. In 47th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2020, Valencia, Spain, May 30 - June 3, 2020, pp. 377-390, IEEE, 2020.
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• Karthik Ganesan, Joshua San Miguel, and Natalie D. Enright Jerger. The What's Next Intermittent Computing Architecture. In 25th IEEE International Symposium on High Performance Computer Architecture, HPCA 2019, Washington, DC, USA, February 16-20, 2019, pp. 211-223, IEEE, 2019.
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• Natalie D. Enright Jerger and Joshua San Miguel. Approximate Cache Architectures. In Sherief Reda and Muhammad Shafique, editors, Approximate Circuits, Methodologies and CAD, pp. 399-416, Springer, 2019.
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• Mayank Parasar, Natalie D. Enright Jerger, Paul V. Gratz, Joshua San Miguel, and Tushar Krishna. SWAP: Synchronized Weaving of Adjacent Packets for Network Deadlock Resolution. In Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2019, Columbus, OH, USA, October 12-16, 2019, pp. 873-885, ACM, 2019.
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• Di Wu, Tianen Chen, Chienfu Chen, Oghenefego Ahia, Joshua San Miguel, Mikko H. Lipasti, and Younghyun Kim. SECO: A Scalable Accuracy Approximate Exponential Function Via Cross-Layer Optimization. In 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019, Lausanne, Switzerland, July 29-31, 2019, pp. 1-6, IEEE, 2019.
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• Di Wu and Joshua San Miguel. In-Stream Stochastic Division and Square Root via Correlation. In Proceedings of the 56th Annual Design Automation Conference 2019, DAC 2019, Las Vegas, NV, USA, June 02-06, 2019, pp. 162:1-162:6, ACM, 2019.
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• Natalie D. Enright Jerger and Joshua San Miguel. Approximate Computing. IEEE Micro, 38(4):8-10, 2018.
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• Joshua San Miguel, Karthik Ganesan, Mario Badr, and Natalie D. Enright Jerger. The EH Model: Analytical Exploration of Energy-Harvesting Architectures. IEEE Comput. Archit. Lett., 17(1):76-79, 2018.
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• Joshua San Miguel, Karthik Ganesan, Mario Badr, Chunqiu Xia, Rose Li, Hsuan Hsiao, and Natalie D. Enright Jerger. The EH Model: Early Design Space Exploration of Intermittent Processor Architectures. In 51st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2018, Fukuoka, Japan, October 20-24, 2018, pp. 600-612, IEEE Computer Society, 2018.
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• Thierry Moreau, Joshua San Miguel, Mark Wyse, James Bornholt, Armin Alaghi, Luis Ceze, Natalie D. Enright Jerger, and Adrian Sampson. A Taxonomy of General Purpose Approximate Computing Techniques. IEEE Embed. Syst. Lett., 10(1):2-5, 2018.
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• Zimo Li, Joshua San Miguel, and Natalie D. Enright Jerger. The runahead network-on-chip. In 2016 IEEE International Symposium on High Performance Computer Architecture, HPCA 2016, Barcelona, Spain, March 12-16, 2016, pp. 333-344, IEEE Computer Society, 2016.
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• Joshua San Miguel and Natalie D. Enright Jerger. The Anytime Automaton. In 43rd ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2016, Seoul, South Korea, June 18-22, 2016, pp. 545-557, IEEE Computer Society, 2016.
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• Joshua San Miguel, Jorge Albericio, Natalie D. Enright Jerger, and Aamer Jaleel. The Bunker Cache for spatio-value approximation. In 49th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2016, Taipei, Taiwan, October 15-19, 2016, pp. 43:1-43:12, IEEE Computer Society, 2016.
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• André Seznec, Joshua San Miguel, and Jorge Albericio. Practical Multidimensional Branch Prediction. IEEE Micro, 36(3):10-19, 2016.
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• Joshua San Miguel, Jorge Albericio, Andreas Moshovos, and Natalie D. Enright Jerger. Doppelgänger: a cache for approximate computing. In Proceedings of the 48th International Symposium on Microarchitecture, MICRO 2015, Waikiki, HI, USA, December 5-9, 2015, pp. 50-61, ACM, 2015.
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• Joshua San Miguel and Natalie D. Enright Jerger. Data Criticality in Network-On-Chip Design. In Proceedings of the 9th International Symposium on Networks-on-Chip, NOCS 2015, Vancouver, BC, Canada, September 28-30, 2015, pp. 22:1-22:8, ACM, 2015.
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• André Seznec, Joshua San Miguel, and Jorge Albericio. The inner most loop iteration counter: a new dimension in branch history. In Proceedings of the 48th International Symposium on Microarchitecture, MICRO 2015, Waikiki, HI, USA, December 5-9, 2015, pp. 347-357, ACM, 2015.
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• Jorge Albericio, Joshua San Miguel, Natalie D. Enright Jerger, and Andreas Moshovos. Wormhole: Wisely Predicting Multidimensional Branches. In 47th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2014, Cambridge, United Kingdom, December 13-17, 2014, pp. 509-520, IEEE Computer Society, 2014.
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• Joshua San Miguel, Mario Badr, and Natalie D. Enright Jerger. Load Value Approximation. In 47th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2014, Cambridge, United Kingdom, December 13-17, 2014, pp. 127-139, IEEE Computer Society, 2014.
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Sankaralingam

• Newsha Ardalani, Urmish Thakker, Aws Albarghouthi, and Karu Sankaralingam. A Static Analysis-based Cross-Architecture Performance Prediction Using Machine Learning. CoRR, abs/1906.07840, 2019.
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• Yuxi Chen, Shu Wang, Shan Lu, and Karthikeyan Sankaralingam. Applying Transactional Memory for Concurrency-Bug Failure Recovery in Production Runs. IEEE Trans. Parallel Distributed Syst., 30(5):990-1006, 2019.
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• Tony Nowatzki, Vinay Gangadhar, and Karthikeyan Sankaralingam. Heterogeneous Von Neumann/dataflow microprocessors. Commun. ACM, 62(6):83-91, 2019.
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• Yuxi Chen, Shu Wang, Shan Lu, and Karthikeyan Sankaralingam. Applying Hardware Transactional Memory for Concurrency-Bug Failure Recovery in Production Runs. In 2018 USENIX Annual Technical Conference, USENIX ATC 2018, Boston, MA, USA, July 11-13, 2018, pp. 837-850, USENIX Association, 2018.
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• Tony Nowatzki, Newsha Ardalani, Karthikeyan Sankaralingam, and Jian Weng. Hybrid optimization/heuristic instruction scheduling for programmable accelerator codesign. In Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, PACT 2018, Limassol, Cyprus, November 01-04, 2018, pp. 36:1-36:15, ACM, 2018.
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• Thiruvengadam Vijayaraghavan, Amit Rajesh, and Karthikeyan Sankaralingam. MPU-BWM: Accelerating Sequence Alignment. IEEE Comput. Archit. Lett., 17(2):179-182, 2018.
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• Luis Ceze, Mark D. Hill, Karthikeyan Sankaralingam, and Thomas F. Wenisch. Democratizing Design for Future Computing Platforms. CoRR, abs/1706.08597, 2017.
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• Gagan Gupta, Tony Nowatzki, Vinay Gangadhar, and Karthikeyan Sankaralingam. Kickstarting Semiconductor Innovation with Open Source Hardware. Computer, 50(6):50-59, 2017.
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• Tony Nowatzki, Vinay Gangadhar, Karthikeyan Sankaralingam, and Greg Wright. Domain Specialization Is Generally Unnecessary for Accelerators. IEEE Micro, 37(3):40-50, 2017.
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• Tony Nowatzki, Vinay Gangadhar, Newsha Ardalani, and Karthikeyan Sankaralingam. Stream-Dataflow Acceleration. In Proceedings of the 44th Annual International Symposium on Computer Architecture, ISCA 2017, Toronto, ON, Canada, June 24-28, 2017, pp. 416-429, ACM, 2017.
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• Babak Falsafi, Mircea Stan, Kevin Skadron, Nuwan Jayasena, Yunji Chen, Jinhua Tao, Ravi Nair, Jaime H. Moreno, Naveen Muralimanohar, Karthikeyan Sankaralingam, and Cristian Estan. Near-Memory Data Services. IEEE Micro, 36(1):6-13, 2016.
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• Gagan Gupta, Tony Nowatzki, Vinay Gangadhar, and Karthikeyan Sankaralingam. Open-source Hardware: Opportunities and Challenges. CoRR, abs/1606.01980, 2016.
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• Chen-Han Ho, Sung Jin Kim, and Karthikeyan Sankaralingam. Accelerating the Accelerator Memory Interface with Access-Execute and Dataflow. IEEE Micro, 36(3):31-41, 2016.
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• Tony Nowatzki, Vinay Gangadhar, and Karthikeyan Sankaralingam. A Heterogeneous Von Neumann/Explicit Dataflow Processor. IEEE Micro, 36(3):20-30, 2016.
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• Tony Nowatzki and Karthikeyan Sankaralingam. Analyzing Behavior Specialized Acceleration. In Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2016, Atlanta, GA, USA, April 2-6, 2016, pp. 697-711, ACM, 2016.
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• Tony Nowatzki and Karthikeyan Sankaralingam. Modularizing the microprocessor core to outperform traditional out-of-order. In 2016 IEEE Hot Chips 28 Symposium (HCS), Cupertino, CA, USA, August 21-23, 2016, pp. 1-4, IEEE, 2016.
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• Tony Nowatzki, Vinay Gangadhar, Karthikeyan Sankaralingam, and Greg Wright. Pushing the limits of accelerator efficiency while retaining programmability. In 2016 IEEE International Symposium on High Performance Computer Architecture, HPCA 2016, Barcelona, Spain, March 12-16, 2016, pp. 27-39, IEEE Computer Society, 2016.
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• Newsha Ardalani, Clint Lestourgeon, Karthikeyan Sankaralingam, and Xiaojin Zhu. Cross-architecture performance prediction (XAPP) using CPU code to predict GPU performance. In Proceedings of the 48th International Symposium on Microarchitecture, MICRO 2015, Waikiki, HI, USA, December 5-9, 2015, pp. 725-737, ACM, 2015.
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• Raghuraman Balasubramanian, Vinay Gangadhar, Ziliang Guo, Chen-Han Ho, Cherin Joseph, Jaikrishnan Menon, Mario Paulo Drumond, Robin Paul, Sharath Prasad, Pradip Valathol, and Karthikeyan Sankaralingam. Enabling GPGPU Low-Level Hardware Explorations with MIAOW: An Open-Source RTL Implementation of a GPGPU. ACM Trans. Archit. Code Optim., 12(2):21:21:1-21:21:25, 2015.
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• Raghuraman Balasubramanian, Vinay Gangadhar, Ziliang Guo, Chen-Han Ho, Cherin Joseph, Jaikrishnan Menon, Mario Paulo Drumond, Robin Paul, Sharath Prasad, Pradip Valathol, and Karthikeyan Sankaralingam. MIAOW - An open source RTL implementation of a GPGPU. In 2015 IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS XVIII, Yokohama, Japan, April 13-15, 2015, pp. 1-3, IEEE Computer Society, 2015.
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• Emily R. Blem, Jaikrishnan Menon, Thiruvengadam Vijayaraghavan, and Karthikeyan Sankaralingam. ISA Wars: Understanding the Relevance of ISA being RISC or CISC to Performance, Power, and Energy on Modern Architectures. ACM Trans. Comput. Syst., 33(1):3:1-3:34, 2015.
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• Dongdong Deng, Guoliang Jin, Marc de Kruijf, Ang Li, Ben Liblit, Shan Lu, Shanxiang Qi, Jinglei Ren, Karthikeyan Sankaralingam, Linhai Song, Yongwei Wu, Mingxing Zhang, Wei Zhang, and Weimin Zheng. Fixing, preventing, and recovering from concurrency bugs. Sci. China Inf. Sci., 58(5):1-18, 2015.
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• Vinay Gangadhar, Raghuraman Balasubramanian, Mario Drumond, Ziliang Guo, Jai Menon, Cherin Joseph, Robin Prakash, Sharath Prasad, Pradip Vallathol, and Karu Sankaralingam. MIAOW: An open source GPGPU. In 2015 IEEE Hot Chips 27 Symposium (HCS), Cupertino, CA, USA, August 22-25, 2015, pp. 1-43, IEEE, 2015.
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• Chen-Han Ho, Sung Jin Kim, and Karthikeyan Sankaralingam. Efficient execution of memory access phases using dataflow specialization. In Proceedings of the 42nd Annual International Symposium on Computer Architecture, Portland, OR, USA, June 13-17, 2015, pp. 118-130, ACM, 2015.
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• Chen-Han Ho, Venkatraman Govindaraju, Tony Nowatzki, Ranjini Nagaraju, Zachary Marzec, Preeti Agarwal, Chris Frericks, Ryan Cofell, and Karthikeyan Sankaralingam. Performance evaluation of a DySER FPGA prototype system spanning the compiler, microarchitecture, and hardware implementation. In 2015 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2015, Philadelphia, PA, USA, March 29-31, 2015, pp. 203-214, IEEE Computer Society, 2015.
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• Tony Nowatzki, Venkatraman Govindaraju, and Karthikeyan Sankaralingam. A Graph-Based Program Representation for Analyzing Hardware Specialization Approaches. IEEE Comput. Archit. Lett., 14(2):94-98, 2015.
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• Tony Nowatzki, Jaikrishnan Menon, Chen-Han Ho, and Karthikeyan Sankaralingam. Architectural Simulators Considered Harmful. IEEE Micro, 35(6):4-12, 2015.
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• Tony Nowatzki, Vinay Gangadhar, and Karthikeyan Sankaralingam. Exploring the potential of heterogeneous von neumann/dataflow execution models. In Proceedings of the 42nd Annual International Symposium on Computer Architecture, Portland, OR, USA, June 13-17, 2015, pp. 298-310, ACM, 2015.
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• Amir Yazdanbakhsh, Raghuraman Balasubramanian, Tony Nowatzki, and Karthikeyan Sankaralingam. Comprehensive Circuit Failure Prediction for Logic and SRAM Using Virtual Aging. IEEE Micro, 35(6):24-36, 2015.
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• Raghuraman Balasubramanian and Karthikeyan Sankaralingam. Understanding the impact of gate-level physical reliability effects on whole program execution. In 20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014, Orlando, FL, USA, February 15-19, 2014, pp. 60-71, IEEE Computer Society, 2014.
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• Raghuraman Balasubramanian, Zachary York, Matthew Doran, Aritra Biswas, Timur Girgin, and Karthikeyan Sankaralingam. Hands-on introduction to computer science at the freshman level. In The 45th ACM Technical Symposium on Computer Science Education, SIGCSE 2014, Atlanta, GA, USA, March 5-8, 2014, pp. 235-240, ACM, 2014.
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• Jaikrishnan Menon, Lorenzo De Carli, Vijayraghavan Thiruvengadam, Karthikeyan Sankaralingam, and Cristian Estan. Memory processing units. In 2014 IEEE Hot Chips 26 Symposium (HCS), Cupertino, CA, USA, August 10-12, 2014, pp. 1, IEEE, 2014.
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• Tony Nowatzki, Michael Sartin-Tarm, Lorenzo De Carli, Karthikeyan Sankaralingam, Cristian Estan, and Behnam Robatmili. A Scheduling Framework for Spatial Architectures Across Multiple Constraint-Solving Theories. ACM Trans. Program. Lang. Syst., 37(1):2:1-2:30, 2014.
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• Raghuraman Balasubramanian and Karthikeyan Sankaralingam. Virtually-aged sampling DMR: unifying circuit failure prediction and circuit failure detection. In The 46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-46, Davis, CA, USA, December 7-11, 2013, pp. 123-135, ACM, 2013.
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• Emily R. Blem, Hadi Esmaeilzadeh, Renée St. Amant, Karthikeyan Sankaralingam, and Doug Burger. Multicore Model from Abstract Single Core Inputs. IEEE Comput. Archit. Lett., 12(2):59-62, 2013.
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• Emily R. Blem, Jaikrishnan Menon, and Karthikeyan Sankaralingam. Power struggles: Revisiting the RISC vs. CISC debate on contemporary ARM and x86 architectures. In 19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013, Shenzhen, China, February 23-27, 2013, pp. 1-12, IEEE Computer Society, 2013.
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• Hadi Esmaeilzadeh, Emily R. Blem, Renée St. Amant, Karthikeyan Sankaralingam, and Doug Burger. Power challenges may end the multicore era. Commun. ACM, 56(2):93-102, 2013.
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• Venkatraman Govindaraju, Tony Nowatzki, and Karthikeyan Sankaralingam. Breaking SIMD shackles with an exposed flexible microarchitecture and the access execute PDG. In Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, Edinburgh, United Kingdom, September 7-11, 2013, pp. 341-351, IEEE Computer Society, 2013.
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• Sung Jin Kim, Lorenzo De Carli, Karthikeyan Sankaralingam, and Cristian Estan. SWSL: SoftWare Synthesis for network Lookup. In Symposium on Architecture for Networking and Communications Systems, ANCS '13, San Jose, CA, USA, October 21-22, 2013, pp. 191-201, IEEE Computer Society, 2013.
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• Marc de Kruijf and Karthikeyan Sankaralingam. Idempotent code generation: Implementation, analysis, and evaluation. In Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization, CGO 2013, Shenzhen, China, February 23-27, 2013, pp. 27:1-27:12, IEEE Computer Society, 2013.
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• Tony Nowatzki, Michael C. Ferris, Karu Sankaralingam, Cristian Estan, Nilay Vaish, and David A. Wood. Optimization and Mathematical Modeling in Computer Architecture, Synthesis Lectures on Computer Architecture, Morgan \& Claypool Publishers, 2013.
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• Tony Nowatzki, Michael Sartin-Tarm, Lorenzo De Carli, Karthikeyan Sankaralingam, Cristian Estan, and Behnam Robatmili. A general constraint-centric scheduling framework for spatial architectures. In ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI '13, Seattle, WA, USA, June 16-19, 2013, pp. 495-506, ACM, 2013.
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• Karthikeyan Sankaralingam. Dynamic hardware specialization-using moore's bounty without burning the chip down. In International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2013, Montreal, QC, Canada, September 29 - October 4, 2013, pp. 17:1, IEEE, 2013.
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• Michael Sartin-Tarm, Tony Nowatzki, Lorenzo De Carli, Karthikeyan Sankaralingam, and Cristian Estan. Constraint centric scheduling guide. SIGARCH Comput. Archit. News, 41(2):17-21, 2013.
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• Wei Zhang, Marc de Kruijf, Ang Li, Shan Lu, and Karthikeyan Sankaralingam. ConAir: featherweight concurrency bug recovery via single-threaded idempotent execution. In Architectural Support for Programming Languages and Operating Systems, ASPLOS 2013, Houston, TX, USA, March 16-20, 2013, pp. 113-126, ACM, 2013.
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• Jesse Benson, Ryan Cofell, Chris Frericks, Chen-Han Ho, Venkatraman Govindaraju, Tony Nowatzki, and Karthikeyan Sankaralingam. Design, integration and implementation of the DySER hardware accelerator into OpenSPARC. In 18th IEEE International Symposium on High Performance Computer Architecture, HPCA 2012, New Orleans, LA, USA, 25-29 February, 2012, pp. 115-126, IEEE Computer Society, 2012.
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• Hadi Esmaeilzadeh, Emily R. Blem, Renée St. Amant, Karthikeyan Sankaralingam, and Doug Burger. Dark Silicon and the End of Multicore Scaling. IEEE Micro, 32(3):122-134, 2012.
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• Hadi Esmaeilzadeh, Emily R. Blem, Renée St. Amant, Karthikeyan Sankaralingam, and Doug Burger. Power Limitations and Dark Silicon Challenge the Future of Multicore. ACM Trans. Comput. Syst., 30(3):11:1-11:27, 2012.
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• Venkatraman Govindaraju, Chen-Han Ho, Tony Nowatzki, Jatin Chhugani, Nadathur Satish, Karthikeyan Sankaralingam, and Changkyu Kim. DySER: Unifying Functionality and Parallelism Specialization for Energy-Efficient Computing. IEEE Micro, 32(5):38-51, 2012.
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• Eric N. Harris, Samuel L. Wasmundt, Lorenzo De Carli, Karthikeyan Sankaralingam, and Cristian Estan. LEAP: latency- energy- and area-optimized lookup pipeline. In Symposium on Architecture for Networking and Communications Systems, ANCS '12, Austin, TX, USA - October 29 - 30, 2012, pp. 175-186, ACM, 2012.
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• Chen-Han Ho, Marc de Kruijf, Karthikeyan Sankaralingam, Barry Rountree, Martin Schulz, and Bronis R. de Supinski. Mechanisms and Evaluation of Cross-Layer Fault-Tolerance for Supercomputing. In 41st International Conference on Parallel Processing, ICPP 2012, Pittsburgh, PA, USA, September 10-13, 2012, pp. 510-519, IEEE Computer Society, 2012.
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• Marc de Kruijf, Karthikeyan Sankaralingam, and Somesh Jha. Static analysis and compiler design for idempotent processing. In ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI '12, Beijing, China - June 11 - 16, 2012, pp. 475-486, ACM, 2012.
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• Jaikrishnan Menon, Marc de Kruijf, and Karthikeyan Sankaralingam. iGPU: Exception support and speculative execution on GPUs. In 39th International Symposium on Computer Architecture (ISCA 2012), June 9-13, 2012, Portland, OR, USA, pp. 72-83, IEEE Computer Society, 2012.
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• Hadi Esmaeilzadeh, Emily R. Blem, Renée St. Amant, Karthikeyan Sankaralingam, and Doug Burger. Dark silicon and the end of multicore scaling. In 38th International Symposium on Computer Architecture (ISCA 2011), June 4-8, 2011, San Jose, CA, USA, pp. 365-376, ACM, 2011.
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• Venkatraman Govindaraju, Chen-Han Ho, and Karthikeyan Sankaralingam. Dynamically Specialized Datapaths for energy efficient computing. In 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), February 12-16 2011, San Antonio, Texas, USA, pp. 503-514, IEEE Computer Society, 2011.
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• Chen-Han Ho, Garret Staus, Aaron Ullmer, and Karu Sankaralingam. Exploring the Interaction Between Device Lifetime Reliability and Security Vulnerabilities. IEEE Comput. Archit. Lett., 10(2):37-40, 2011.
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• Marc de Kruijf and Karthikeyan Sankaralingam. Idempotent processor architecture. In 44rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2011, Porto Alegre, Brazil, December 3-7, 2011, pp. 140-151, ACM, 2011.
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• Shuou Nomura, Matthew D. Sinclair, Chen-Han Ho, Venkatraman Govindaraju, Marc de Kruijf, and Karthikeyan Sankaralingam. Sampling + DMR: practical and low-overhead permanent fault detection. In 38th International Symposium on Computer Architecture (ISCA 2011), June 4-8, 2011, San Jose, CA, USA, pp. 201-212, ACM, 2011.
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• Nilay Vaish, Thawan Kooburat, Lorenzo De Carli, Karthikeyan Sankaralingam, and Cristian Estan. Experiences in Co-designing a Packet Classification Algorithm and a Flexible Hardware Platform. In 2011 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), Brooklyn, NY, USA, October 3-4, 2011, pp. 189-199, IEEE Computer Society, 2011.
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• Marc de Kruijf, Shuou Nomura, and Karthikeyan Sankaralingam. A unified model for timing speculation: Evaluating the impact of technology scaling, CMOS design style, and fault recovery mechanism. In Proceedings of the 2010 IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2010, Chicago, IL, USA, June 28 - July 1 2010, pp. 487-496, IEEE Computer Society, 2010.
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• Marc de Kruijf, Shuou Nomura, and Karthikeyan Sankaralingam. Relax: an architectural framework for software recovery of hardware faults. In 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 497-508, ACM, 2010.
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• Amit Kumar, Lorenzo De Carli, Sung Jin Kim, Marc de Kruijf, Karthikeyan Sankaralingam, Cristian Estan, and Somesh Jha. Design and implementation of the PLUG architecture for programmable and efficient network lookups. In 19th International Conference on Parallel Architectures and Compilation Techniques, PACT 2010, Vienna, Austria, September 11-15, 2010, pp. 331-342, ACM, 2010.
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• Shuou Nomura, Karthikeyan Sankaralingam, and Ranganathan Sankaralingam. A fast and highly accurate path delay emulation framework for logic-emulation of timing speculation. In 2011 IEEE International Test Conference, ITC 2010, Austin, TX, USA, November 2-4, 2010, pp. 635-644, IEEE Computer Society, 2010.
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• Shuou Nomura, Karthikeyan Sankaralingam, and Ranganathan Sankaralingam. A fast and highly accurate path delay emulation framework for logic-emulation of timing speculation. In 2011 IEEE International Test Conference, ITC 2010, Austin, TX, USA, November 2-4, 2010, pp. 635-644, IEEE Computer Society, 2010.
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• Lorenzo De Carli, Yi Pan, Amit Kumar, Cristian Estan, and Karthikeyan Sankaralingam. PLUG: flexible lookup modules for rapid deployment of new protocols in high-speed routers. In Proceedings of the ACM SIGCOMM 2009 Conference on Applications, Technologies, Architectures, and Protocols for Computer Communications, Barcelona, Spain, August 16-21, 2009, pp. 207-218, ACM, 2009.
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• Marc de Kruijf and Karthikeyan Sankaralingam. MapReduce for the Cell Broadband Engine Architecture. IBM J. Res. Dev., 53(5):10, 2009.
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• Randy Smith, Neelam Goyal, Justin Ormont, Karthikeyan Sankaralingam, and Cristian Estan. Evaluating GPUs for network packet signature matching. In IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2009, April 26-28, 2009, Boston, Massachusetts, USA, Proceedings, pp. 175-184, IEEE Computer Society, 2009.
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• Venkatraman Govindaraju, Peter Djeu, Karthikeyan Sankaralingam, Mary K. Vernon, and William R. Mark. Toward a multicore architecture for real-time ray-tracing. In 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy, pp. 176-187, IEEE Computer Society, 2008.
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• Paul Gratz, Changkyu Kim, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Stephen W. Keckler, and Doug Burger. On-Chip Interconnection Networks of the TRIPS Chip. IEEE Micro, 27(5):41-50, 2007.
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• Paul Gratz, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Robert G. McDonald, Stephen W. Keckler, and Doug Burger. Implementation and Evaluation of a Dynamically Routed Processor Operand Network. In First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 7-17, IEEE Computer Society, 2007.
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• Daniel Sánchez, Luke Yen, Mark D. Hill, and Karthikeyan Sankaralingam. Implementing Signatures for Transactional Memory. In 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 1-5 December 2007, Chicago, Illinois, USA, pp. 123-133, IEEE Computer Society, 2007.
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• Karthikeyan Sankaralingam, Ramadass Nagarajan, Robert G. McDonald, Rajagopalan Desikan, Saurabh Drolia, M. S. Govindan, Paul Gratz, Divya Gulati, Heather Hanson, Changkyu Kim, Haiming Liu, Nitya Ranganathan, Simha Sethumadhavan, Sadia Sharif, Premkishore Shivakumar, Stephen W. Keckler, and Doug Burger. Distributed Microarchitectural Protocols in the TRIPS Prototype Processor. In 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 9-13 December 2006, Orlando, Florida, USA, pp. 480-491, IEEE Computer Society, 2006.
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• Aaron Smith, Ramadass Nagarajan, Karthikeyan Sankaralingam, Robert G. McDonald, Doug Burger, Stephen W. Keckler, and Kathryn S. McKinley. Dataflow Predication. In 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 9-13 December 2006, Orlando, Florida, USA, pp. 89-102, IEEE Computer Society, 2006.
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• Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Nitya Ranganathan, Doug Burger, Stephen W. Keckler, Robert G. McDonald, and Charles R. Moore. TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP. ACM Trans. Archit. Code Optim., 1(1):62-93, 2004.
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• Karthikeyan Sankaralingam, Madhulika Yalamanchi, Simha Sethumadhavan, and James C. Browne. Pagerank Computation and Keyword Search on Distributed Systems and P2P Networks. J. Grid Comput., 1(3):291-307, 2003.
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• Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, and Charles R. Moore. Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture. IEEE Micro, 23(6):46-51, 2003.
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• Karthikeyan Sankaralingam, Simha Sethumadhavan, and James C. Browne. Distributed Pagerank for P2P Systems. In 12th International Symposium on High-Performance Distributed Computing (HPDC-12 2003), 22-24 June 2003, Seattle, WA, USA, pp. 58-69, IEEE Computer Society, 2003.
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• Karthikeyan Sankaralingam, Vincent Ajay Singh, Stephen W. Keckler, and Doug Burger. Routed Inter-ALU Networks for ILP Scalability and Performance. In 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 170, IEEE Computer Society, 2003.
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• Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, and Charles R. Moore. Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture. In 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA, pp. 422-433, IEEE Computer Society, 2003.
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• Karthikeyan Sankaralingam, Stephen W. Keckler, William R. Mark, and Doug Burger. Universal Mechanisms for Data-Parallel Architectures. In Proceedings of the 36th Annual International Symposium on Microarchitecture, San Diego, CA, USA, December 3-5, 2003, pp. 303-314, IEEE Computer Society, 2003.
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• Ramadass Nagarajan, Karthikeyan Sankaralingam, Doug Burger, and Stephen W. Keckler. A design space evaluation of grid processor architectures. In Proceedings of the 34th Annual International Symposium on Microarchitecture, Austin, Texas, USA, December 1-5, 2001, pp. 40-51, ACM/IEEE Computer Society, 2001.
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Sinclair

• Johnathan Alsop, Weon Taek Na, Matthew D. Sinclair, Samuel Grayson, and Sarita V. Adve. A Case for Fine-grain Coherence Specialization in Heterogeneous Systems. CoRR, abs/2104.11678, 2021.
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• Bobby R. Bruce, Ayaz Akram, Hoa Nguyen, Kyle Roarty, Mahyar Samani, Marjan Fariborz, Trivikram Reddy, Matthew D. Sinclair, and Jason Lowe-Power. Enabling Reproducible and Agile Full-System Simulation. In IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2021, Stony Brook, NY, USA, March 28-30, 2021, pp. 183-193, IEEE, 2021.
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• Suchita Pati, Shaizeen Aga, Nuwan Jayasena, and Matthew D. Sinclair. Demystifying BERT: Implications for Accelerator Design. CoRR, abs/2104.08335, 2021.
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• Tsung Tai Yeh, Matthew D. Sinclair, Bradford M. Beckmann, and Timothy G. Rogers. Deadline-Aware Offloading for High-Throughput Accelerators. In IEEE International Symposium on High-Performance Computer Architecture, HPCA 2021, Seoul, South Korea, February 27 - March 3, 2021, pp. 479-492, IEEE, 2021.
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• Yuan-Hsi Chou, Christopher Ng, Shaylin Cattell, Jeremy Intan, Matthew D. Sinclair, Joseph Devietti, Timothy G. Rogers, and Tor M. Aamodt. Deterministic Atomic Buffering. In 53rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2020, Athens, Greece, October 17-21, 2020, pp. 981-995, IEEE, 2020.
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• Alexandru Dutu, Matthew D. Sinclair, Bradford M. Beckmann, David A. Wood, and Marcus Chow. Independent Forward Progress of Work-groups. In 47th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2020, Valencia, Spain, May 30 - June 3, 2020, pp. 1022-1035, IEEE, 2020.
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• Muhammad Huzaifa, Johnathan Alsop, Abdulrahman Mahmoud, Giordano Salvador, Matthew D. Sinclair, and Sarita V. Adve. Inter-kernel Reuse-aware Thread Block Scheduling. ACM Trans. Archit. Code Optim., 17(3):24:1-24:27, 2020.
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• Jason Lowe-Power, Abdul Mutaal Ahmad, Ayaz Akram, Mohammad Alian, Rico Amslinger, Matteo Andreozzi, Adrià Armejach, Nils Asmussen, Srikant Bharadwaj, Gabe Black, Gedare Bloom, Bobby R. Bruce, Daniel Rodrigues Carvalho, Jerónimo Castrillón, Lizhong Chen, Nicolas Derumigny, Stephan Diestelhorst, Wendy Elsasser, Marjan Fariborz, Amin Farmahini Farahani, Pouya Fotouhi, Ryan Gambord, Jayneel Gandhi, Dibakar Gope, Thomas Grass, Bagus Hanindhito, Andreas Hansson, Swapnil Haria, Austin Harris, Timothy Hayes, Adrian Herrera, Matthew Horsnell, Syed Ali Raza Jafri, Radhika Jagtap, Hanhwi Jang, Reiley Jeyapaul, Timothy M. Jones, Matthias Jung, Subash Kannoth, Hamidreza Khaleghzadeh, Yuetsu Kodama, Tushar Krishna, Tommaso Marinelli, Christian Menard, Andrea Mondelli, Tiago Mück, Omar Naji, Krishnendra Nathella, Hoa Nguyen, Nikos Nikoleris, Lena E. Olson, Marc S. Orr, Binh Pham, Pablo Prieto, Trivikram Reddy, Alec Roelke, Mahyar Samani, Andreas Sandberg, Javier Setoain, Boris Shingarov, Matthew D. Sinclair, Tuan Ta, Rahul Thakur, Giacomo Travaglini, Michael Upton, Nilay Vaish, Ilias Vougioukas, Zhengrong Wang, Norbert Wehn, Christian Weis, David A. Wood, Hongil Yoon, and Éder F. Zulian. The gem5 Simulator: Version 20.0+. CoRR, abs/2007.03152, 2020.
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• Suchita Pati, Shaizeen Aga, Matthew D. Sinclair, and Nuwan Jayasena. SeqPoint: Identifying Representative Iterations of Sequence-Based Neural Networks. In IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2020, Boston, MA, USA, August 23-25, 2020, pp. 69-80, IEEE, 2020.
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• Suchita Pati, Shaizeen Aga, Matthew D. Sinclair, and Nuwan Jayasena. SeqPoint: Identifying Representative Iterations of Sequence-based Neural Networks. CoRR, abs/2007.10459, 2020.
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• Giordano Salvador, Wesley H. Darvin, Muhammad Huzaifa, Johnathan Alsop, Matthew D. Sinclair, and Sarita V. Adve. Specializing Coherence, Consistency, and Push/Pull for GPU Graph Analytics. In IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2020, Boston, MA, USA, August 23-25, 2020, pp. 123-125, IEEE, 2020.
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• Giordano Salvador, Wesley H. Darvin, Muhammad Huzaifa, Johnathan Alsop, Matthew D. Sinclair, and Sarita V. Adve. Specializing Coherence, Consistency, and Push/Pull for GPU Graph Analytics. CoRR, abs/2002.10245, 2020.
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• Johnathan Alsop, Xianwei Zhang, Tsung Tai Yeh, Bradford M. Beckmann, Matthew D. Sinclair, Srikant Bharadwaj, Alexandru Dutu, Anthony Gutierrez, Onur Kayiran, Michael LeBeane, Brandon Potter, and Sooraj Puthoor. Optimizing GPU Cache Policies for MI Workloads. In IEEE International Symposium on Workload Characterization, IISWC 2019, Orlando, FL, USA, November 3-5, 2019, pp. 243-248, IEEE, 2019.
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• Johnathan Alsop, Matthew D. Sinclair, Srikant Bharadwaj, Alexandru Dutu, Anthony Gutierrez, Onur Kayiran, Michael LeBeane, Sooraj Puthoor, Xianwei Zhang, Tsung Tai Yeh, and Bradford M. Beckmann. Optimizing GPU Cache Policies for MI Workloads. CoRR, abs/1910.00134, 2019.
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• Jonathan Lew, Deval A. Shah, Suchita Pati, Shaylin Cattell, Mengchi Zhang, Amruth Sandhupatla, Christopher Ng, Negar Goli, Matthew D. Sinclair, Timothy G. Rogers, and Tor M. Aamodt. Analyzing Machine Learning Workloads Using a Detailed GPU Simulator. In IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2019, Madison, WI, USA, March 24-26, 2019, pp. 151-152, IEEE, 2019.
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• Johnathan Alsop, Matthew D. Sinclair, and Sarita V. Adve. Spandex: A Flexible Interface for Efficient Heterogeneous Coherence. In 45th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2018, Los Angeles, CA, USA, June 1-6, 2018, pp. 261-274, IEEE Computer Society, 2018.
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• Anthony Gutierrez, Bradford M. Beckmann, Alexandru Dutu, Joseph Gross, Michael LeBeane, John Kalamatianos, Onur Kayiran, Matthew Poremba, Brandon Potter, Sooraj Puthoor, Matthew D. Sinclair, Mark Wyse, Jieming Yin, Xianwei Zhang, Akshay Jain, and Timothy G. Rogers. Lost in Abstraction: Pitfalls of Analyzing GPUs at the Intermediate Language Level. In IEEE International Symposium on High Performance Computer Architecture, HPCA 2018, Vienna, Austria, February 24-28, 2018, pp. 608-619, IEEE Computer Society, 2018.
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• Maria Kotsifakou, Prakalp Srivastava, Matthew D. Sinclair, Rakesh Komuravelli, Vikram S. Adve, and Sarita V. Adve. HPVM: heterogeneous parallel virtual machine. In Proceedings of the 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPoPP 2018, Vienna, Austria, February 24-28, 2018, pp. 68-80, ACM, 2018.
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• Jonathan Lew, Deval Shah, Suchita Pati, Shaylin Cattell, Mengchi Zhang, Amruth Sandhupatla, Christopher Ng, Negar Goli, Matthew D. Sinclair, Timothy G. Rogers, and Tor M. Aamodt. Analyzing Machine Learning Workloads Using a Detailed GPU Simulator. CoRR, abs/1811.08933, 2018.
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• Matthew D. Sinclair, Johnathan Alsop, and Sarita V. Adve. HeteroSync: A benchmark suite for fine-grained synchronization on tightly coupled GPUs. In 2017 IEEE International Symposium on Workload Characterization, IISWC 2017, Seattle, WA, USA, October 1-3, 2017, pp. 239-249, IEEE Computer Society, 2017.
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• Matthew D. Sinclair, Johnathan Alsop, and Sarita V. Adve. Chasing Away RAts: Semantics and Evaluation for Relaxed Atomics on Heterogeneous Systems. In Proceedings of the 44th Annual International Symposium on Computer Architecture, ISCA 2017, Toronto, ON, Canada, June 24-28, 2017, pp. 161-174, ACM, 2017.
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• Johnathan Alsop, Matthew D. Sinclair, Rakesh Komuravelli, and Sarita V. Adve. GSI: A GPU Stall Inspector to characterize the sources of memory stalls for tightly coupled GPUs. In 2016 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2016, Uppsala, Sweden, April 17-19, 2016, pp. 172-182, IEEE Computer Society, 2016.
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• Prakalp Srivastava, Maria Kotsifakou, Matthew D. Sinclair, Rakesh Komuravelli, Vikram S. Adve, and Sarita V. Adve. POSTER: hVISC: A Portable Abstraction for Heterogeneous Parallel Systems. In Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, PACT 2016, Haifa, Israel, September 11-15, 2016, pp. 443-445, ACM, 2016.
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• Rakesh Komuravelli, Matthew D. Sinclair, Johnathan Alsop, Muhammad Huzaifa, Maria Kotsifakou, Prakalp Srivastava, Sarita V. Adve, and Vikram S. Adve. Stash: have your scratchpad and cache it too. In Proceedings of the 42nd Annual International Symposium on Computer Architecture, Portland, OR, USA, June 13-17, 2015, pp. 707-719, ACM, 2015.
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• Matthew D. Sinclair, Johnathan Alsop, and Sarita V. Adve. Efficient GPU synchronization without scopes: saying no to complex consistency models. In Proceedings of the 48th International Symposium on Microarchitecture, MICRO 2015, Waikiki, HI, USA, December 5-9, 2015, pp. 647-659, ACM, 2015.
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• Shuou Nomura, Matthew D. Sinclair, Chen-Han Ho, Venkatraman Govindaraju, Marc de Kruijf, and Karthikeyan Sankaralingam. Sampling + DMR: practical and low-overhead permanent fault detection. In 38th International Symposium on Computer Architecture (ISCA 2011), June 4-8, 2011, San Jose, CA, USA, pp. 201-212, ACM, 2011.
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Smith

• James E. Smith. Space-Time Computing with Temporal Neural Networks, Synthesis Lectures on Computer Architecture, Morgan \& Claypool Publishers, 2017.
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• James E. Smith. Research Agenda: Spacetime Computation and the Neocortex. IEEE Micro, 37(1):8-14, 2017.
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• James E. Smith. Efficient digital neurons for large scale cortical architectures. In ACM/IEEE 41st International Symposium on Computer Architecture, ISCA 2014, Minneapolis, MN, USA, June 14-18, 2014, pp. 229-240, IEEE Computer Society, 2014.
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• Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, and James E. Smith. A mechanistic performance model for superscalar out-of-order processors. ACM Trans. Comput. Syst., 27(2):3:1-3:37, 2009.
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• Randy Smith, Neelam Goyal, Justin Ormont, Karthikeyan Sankaralingam, and Cristian Estan. Evaluating GPUs for network packet signature matching. In IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2009, April 26-28, 2009, Boston, Massachusetts, USA, Proceedings, pp. 175-184, IEEE Computer Society, 2009.
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• Nidhi Aggarwal, Jason F. Cantin, Mikko H. Lipasti, and James E. Smith. Power-Efficient DRAM Speculation. In 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 16-20 February 2008, Salt Lake City, UT, USA, pp. 317-328, IEEE Computer Society, 2008.
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• Nidhi Aggarwal, James E. Smith, Kewal K. Saluja, Norman P. Jouppi, and Parthasarathy Ranganathan. Implementing high availability memory with a duplication cache. In 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy, pp. 71-82, IEEE Computer Society, 2008.
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• Stijn Eyerman, Lieven Eeckhout, and James E. Smith. Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis. In High Performance Embedded Architectures and Compilers, Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008, Proceedings, pp. 114-129, Springer, 2008.
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• Kyle J. Nesbit, Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero, and James E. Smith. Multicore Resource Management. IEEE Micro, 28(3):6-16, 2008.
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• Nidhi Aggarwal, Parthasarathy Ranganathan, Norman P. Jouppi, and James E. Smith. Isolation in Commodity Multicore Processors. Computer, 40(6):49-59, 2007.
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• Nidhi Aggarwal, Parthasarathy Ranganathan, Norman P. Jouppi, and James E. Smith. Configurable isolation: building high availability systems with commodity multi-core processors. In 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 470-481, ACM, 2007.
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• Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, and James E. Smith. A Top-Down Approach to Architecting CPI Component Performance Counters. IEEE Micro, 27(1):84-93, 2007.
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• Stijn Eyerman, Lieven Eeckhout, and James E. Smith. Studying Compiler-Microarchitecture Interactions through Interval Analysis. In 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007, pp. 406, IEEE Computer Society, 2007.
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• Tejas Karkhanis and James E. Smith. Automated design of application specific superscalar processors: an analytical approach. In 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 402-411, ACM, 2007.
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• Kyle J. Nesbit, James Laudon, and James E. Smith. Virtual private caches. In 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 57-68, ACM, 2007.
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• Jason F. Cantin, James E. Smith, Mikko H. Lipasti, Andreas Moshovos, and Babak Falsafi. Coarse-Grain Coherence Tracking: RegionScout and Region Coherence Arrays. IEEE Micro, 26(1):70-79, 2006.
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• Jason F. Cantin, Mikko H. Lipasti, and James E. Smith. Stealth prefetching. In Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2006, San Jose, CA, USA, October 21-25, 2006, pp. 274-282, ACM, 2006.
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• Ashutosh S. Dhodapkar and James E. Smith. Tuning adaptive microarchitectures. Int. J. Embed. Syst., 2(1/2):39-50, 2006.
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• Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, and James E. Smith. A performance counter architecture for computing accurate CPI components. In Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2006, San Jose, CA, USA, October 21-25, 2006, pp. 175-184, ACM, 2006.
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• Stijn Eyerman, James E. Smith, and Lieven Eeckhout. Characterizing the branch misprediction penalty. In 2006 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2006, March 19-21, 2006, Austin, Texas, USA, Proceedings, pp. 48-58, IEEE Computer Society, 2006.
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• Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, and James E. Smith. An approach for implementing efficient superscalar CISC processors. In 12th International Symposium on High-Performance Computer Architecture, HPCA-12 2006, Austin, Texas, USA, February 11-15, 2006, pp. 41-52, IEEE Computer Society, 2006.
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• Shiliang Hu and James E. Smith. Reducing Startup Time in Co-Designed Virtual Machines. In 33rd International Symposium on Computer Architecture (ISCA 2006), June 17-21, 2006, Boston, MA, USA, pp. 277-288, IEEE Computer Society, 2006.
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• Kyle J. Nesbit, Nidhi Aggarwal, James Laudon, and James E. Smith. Fair Queuing Memory Systems. In 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 9-13 December 2006, Orlando, Florida, USA, pp. 208-222, IEEE Computer Society, 2006.
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• Aaron Smith, Ramadass Nagarajan, Karthikeyan Sankaralingam, Robert G. McDonald, Doug Burger, Stephen W. Keckler, and Kathryn S. McKinley. Dataflow Predication. In 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 9-13 December 2006, Orlando, Florida, USA, pp. 89-102, IEEE Computer Society, 2006.
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• Joshua J. Yi, Lieven Eeckhout, David J. Lilja, Brad Calder, Lizy Kurian John, and James E. Smith. The Future of Simulation: A Field of Dreams. Computer, 39(11):22-29, 2006.
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• Jason F. Cantin, Mikko H. Lipasti, and James E. Smith. The Complexity of Verifying Memory Coherence and Consistency. IEEE Trans. Parallel Distributed Syst., 16(7):663-671, 2005.
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• Jason F. Cantin, Mikko H. Lipasti, and James E. Smith. Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking. In 32st International Symposium on Computer Architecture (ISCA 2005), 4-8 June 2005, Madison, Wisconsin, USA, pp. 246-257, IEEE Computer Society, 2005.
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• Kyle J. Nesbit and James E. Smith. Data Cache Prefetching Using a Global History Buffer. IEEE Micro, 25(1):90-97, 2005.
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• James E. Smith. A unified view of virtualization. In Proceedings of the 1st International Conference on Virtual Execution Environments, VEE 2005, Chicago, IL, USA, June 11-12, 2005, pp. 1, ACM, 2005.
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• Brad Calder, Daniel Citron, Yale N. Patt, and James E. Smith. The future of simulation: A field of dreams. In 2004 IEEE International Symposium on Performance Analysis of Systems and Software, March 10-12, 2004, Austin, Texas, USA, Proceedings, pp. 169, IEEE Computer Society, 2004.
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• Ashutosh S. Dhodapkar and James E. Smith. Tuning Reconfigurable Microarchitectures for Power Efficiency. In 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, IEEE Computer Society, 2004.
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• Shiliang Hu and James E. Smith. Using Dynamic Binary Translation to Fuse Dependent Instructions. In 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 20-24 March 2004, San Jose, CA, USA, pp. 213-226, IEEE Computer Society, 2004.
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• Tejas Karkhanis and James E. Smith. A First-Order Superscalar Processor Model. In 31st International Symposium on Computer Architecture (ISCA 2004), 19-23 June 2004, Munich, Germany, pp. 338-349, IEEE Computer Society, 2004.
  Details   
• Kyle J. Nesbit, Ashutosh S. Dhodapkar, and James E. Smith. AC/DC: An Adaptive Data Cache Prefetcher. In 13th International Conference on Parallel Architectures and Compilation Techniques (PACT 2004), 29 September - 3 October 2004, Antibes Juan-les-Pins, France, pp. 135-145, IEEE Computer Society, 2004.
  Details   
• Kyle J. Nesbit and James E. Smith. Data Cache Prefetching Using a Global History Buffer. In 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 14-18 February 2004, Madrid, Spain, pp. 96-105, IEEE Computer Society, 2004.
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• James E. Smith. Some Real Observations on Virtual Machines. In Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings, pp. 1, Springer, 2004.
  Details   
• Jason F. Cantin, Mikko H. Lipasti, and James E. Smith. The complexity of verifying memory coherence. In SPAA 2003: Proceedings of the Fifteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures, June 7-9, 2003, San Diego, California, USA (part of FCRC 2003), pp. 254-255, ACM, 2003.
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• Ashutosh S. Dhodapkar and James E. Smith. Comparing Program Phase Detection Techniques. In Proceedings of the 36th Annual International Symposium on Microarchitecture, San Diego, CA, USA, December 3-5, 2003, pp. 217-227, IEEE Computer Society, 2003.
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• Lieven Eeckhout, Sébastien Nussbaum, James E. Smith, and Koen De Bosschere. Statistical Simulation: Adding Efficiency to the Computer Designer's Toolbox. IEEE Micro, 23(5):26-38, 2003.
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• Ho-Seop Kim and James E. Smith. Dynamic Binary Translation for Accumulator-Oriented Architectures. In 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 23-26 March 2003, San Francisco, CA, USA, pp. 25-35, IEEE Computer Society, 2003.
  Details   
• Ho-Seop Kim and James E. Smith. Hardware Support for Control Transfers in Code Caches. In Proceedings of the 36th Annual International Symposium on Microarchitecture, San Diego, CA, USA, December 3-5, 2003, pp. 253-264, IEEE Computer Society, 2003.
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• James E. Smith. Keynote: Is there anything more to learn about high performance processors?. In Proceedings of the 17th Annual International Conference on Supercomputing, ICS 2003, San Francisco, CA, USA, June 23-26, 2003, pp. 75, ACM, 2003.
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• Pradip Bose, David M. Brooks, Alper Buyuktosunoglu, Peter W. Cook, K. Das, Philip G. Emma, Michael Gschwind, Hans M. Jacobson, Tejas Karkhanis, Prabhakar Kudva, Stanley Schuster, James E. Smith, Viji Srinivasan, Victor V. Zyuban, David H. Albonesi, and Sandhya Dwarkadas. Early-Stage Definition of LPX: A Low Power Issue-Execute Processor. In Power-Aware Computer Systems, Second International Workshop, PACS 2002 Cambridge, MA, USA, February 2, 2002, Revised Papers, pp. 1-17, Springer, 2002.
  Details   
• George Cai, Ashutosh S. Dhodapkar, and James E. Smith. Integrated Performance, Power, and Thermal Modeling. J. Circuits Syst. Comput., 11(6):659, 2002.
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• Ashutosh S. Dhodapkar and James E. Smith. Managing Multi-Configuration Hardware via Dynamic Working Set Analysis. In 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA, pp. 233-244, IEEE Computer Society, 2002.
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• Tejas Karkhanis, James E. Smith, and Pradip Bose. Saving energy with just in time instruction delivery. In Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002, pp. 178-183, ACM, 2002.
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• Ho-Seop Kim and James E. Smith. An Instruction Set and Microarchitecture for Instruction Level Distributed Processing. In 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA, pp. 71-81, IEEE Computer Society, 2002.
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• Sébastien Nussbaum and James E. Smith. Statistical Simulation of Symmetric Multiprocessor Systems. In Proceedings 35th Annual Simulation Symposium (ANSS-35 2002), San Diego, California, USA, 14-18 April 2002, pp. 89-97, IEEE Computer Society, 2002.
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• Sébastien Nussbaum and James E. Smith. Modeling Superscalar Processors via Statistical Simulation. In 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 8-12 September 2001, Barcelona, Spain, pp. 15-24, IEEE Computer Society, 2001.
  Details   
• James E. Smith. Instruction-Level Distributed Processing. Computer, 34(4):59-65, 2001.
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• T. N. Vijaykumar, Sridhar Gopal, James E. Smith, and Gurindar S. Sohi. Speculative Versioning Cache. IEEE Trans. Parallel Distributed Syst., 12(12):1305-1317, 2001.
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• Quinn Jacobson and James E. Smith. Trace preconstruction. In 27th International Symposium on Computer Architecture (ISCA 2000), June 10-14, 2000, Vancouver, BC, Canada, pp. 37-46, IEEE Computer Society, 2000.
  Details   
• Eric Rotenberg and James E. Smith. Control Independence in Trace Processors. J. Instr. Level Parallelism, 2, 2000.
  Details   
• James E. Smith. Instruction Level Distributed Processing. In High Performance Computing - HiPC 2000, 7th International Conference, Bangalore, India, December 17-20, 2000, Proceedings, pp. 245-258, Springer, 2000.
  Details   
• James E. Smith. Instruction Level Distributed Processing: Adapting to Future Technology. In High Performance Computing, Third International Symposium, ISHPC 2000, Tokyo, Japan, October 16-18, 2000. Proceedings, pp. 1-6, Springer, 2000.
  Details   
• Quinn Jacobson and James E. Smith. Instruction Pre-Processing in Trace Processors. In Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, Orlando, FL, USA, January 9-12, 1999, pp. 125-129, IEEE Computer Society, 1999.
  Details   
• Eric Rotenberg, Steve Bennett, and James E. Smith. A Trace Cache Microarchitecture and Evaluation. IEEE Trans. Computers, 48(2):111-120, 1999.
  Details   
• Eric Rotenberg, Quinn Jacobson, and James E. Smith. A Study of Control Independence in Superscalar Processors. In Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, Orlando, FL, USA, January 9-12, 1999, pp. 115-124, IEEE Computer Society, 1999.
  Details   
• Eric Rotenberg and James E. Smith. Control Independence in Trace Processors. In Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 32, Haifa, Israel, November 16-18, 1999, pp. 4-15, ACM/IEEE Computer Society, 1999.
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• Yiannakis Sazeides and James E. Smith. Limits of Data Value Predictability. Int. J. Parallel Program., 27(4):229-256, 1999.
  Details   
• Sridhar Gopal, T. N. Vijaykumar, James E. Smith, and Gurindar S. Sohi. Speculative Versioning Cache. In Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Las Vegas, Nevada, USA, January 31 - February 4, 1998, pp. 195-205, IEEE Computer Society, 1998.
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• Yiannakis Sazeides and James E. Smith. Modeling Program Predictability. In Proceedings of the 25th Annual International Symposium on Computer Architecture, ISCA 1998, Barcelona, Spain, June 27 - July 1, 1998, pp. 73-84, IEEE Computer Society, 1998.
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• James E. Smith. Retrospective: A Study of Branch Prediction Strategies. In 25 Years of the International Symposia on Computer Architecture (Selected Papers), pp. 22-23, ACM, 1998.
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• James E. Smith. Retrospective: Decoupled Access/Execute Architectures. In 25 Years of the International Symposia on Computer Architecture (Selected Papers), pp. 27-28, ACM, 1998.
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• James E. Smith. Retrospective: Implementing Precise Interrupts in Pipelined Processors. In 25 Years of the International Symposia on Computer Architecture (Selected Papers), pp. 42, ACM, 1998.
  Details   
• James E. Smith. Decoupled Access/Execute Computer Architectures. In 25 Years of the International Symposia on Computer Architecture (Selected Papers), pp. 231-238, ACM, 1998.
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• Quinn Jacobson, Steve Bennett, Nikhil Sharma, and James E. Smith. Control Flow Speculation in Multiscalar Processors. In Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), San Antonio, Texas, USA, February 1-5, 1997, pp. 218-229, IEEE Computer Society, 1997.
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• Quinn Jacobson, Eric Rotenberg, and James E. Smith. Path-Based Next Trace Prediction. In Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 14-23, ACM/IEEE Computer Society, 1997.
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• Subbarao Palacharla, Norman P. Jouppi, and James E. Smith. Complexity-Effective Superscalar Processors. In Proceedings of the 24th International Symposium on Computer Architecture, Denver, Colorado, USA, June 2-4, 1997, pp. 206-218, ACM, 1997.
  Details   
• Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, and James E. Smith. Trace Processors. In Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 138-148, ACM/IEEE Computer Society, 1997.
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• Yiannakis Sazeides and James E. Smith. The Predictability of Data Values. In Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 248-258, ACM/IEEE Computer Society, 1997.
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• Erik Jacobsen, Eric Rotenberg, and James E. Smith. Assigning Confidence to Conditional Branch Predictions. In Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 142-152, ACM/IEEE Computer Society, 1996.
  Details   
• Eric Rotenberg, Steve Bennett, and James E. Smith. Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching. In Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 24-35, ACM/IEEE Computer Society, 1996.
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• Yiannakis Sazeides, Stamatis Vassiliadis, and James E. Smith. The Performance Potential of Data Dependence Speculation \& Collapsing. In Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 238-247, ACM/IEEE Computer Society, 1996.
  Details   
• James E. Smith and Shlomo Weiss. PowerPC 601 and Alpha 21064: A Tale of Two RISCs. Computer, 27(6):46-58, 1994.
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• Jeffrey D. Gee, Mark D. Hill, Dionisios N. Pnevmatikatos, and Alan Jay Smith. Cache performance of the SPEC92 benchmark suite. IEEE Micro, 13(4):17-27, 1993.
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• Corinna G. Lee and James E. Smith. A Study of Partitioned Vector Register Files. In Proceedings Supercomputing '92, Minneapolis, MN, USA, November 16-20, 1992, pp. 94-103, IEEE Computer Society, 1992.
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• Howard Jay Siegel, Seth Abraham, William L. Bain, Kenneth E. Batcher, Thomas L. Casavant, Doug DeGroot, Jack B. Dennis, David C. Douglas, Tse-Yun Feng, James R. Goodman, Alan Huang, Harry F. Jordan, J. Robert Jamp, Yale N. Patt, Alan Jay Smith, James E. Smith, Lawrence Snyder, Harold S. Stone, Russ Tuck, and Benjamin W. Wah. Report of the Purdue Workshop on Grand Challenges in Computer Architecture for the Support of High Performance Computing. J. Parallel Distributed Comput., 16(3):199-211, 1992.
  Details   
• Howard Jay Siegel, Seth Abraham, William L. Bain, Kenneth E. Batcher, Thomas L. Casavant, Doug DeGroot, Jack B. Dennis, David C. Douglas, Tse-Yun Feng, James R. Goodman, Alan Huang, Harry F. Jordan, J. Robert Jamp, Yale N. Patt, Alan Jay Smith, James E. Smith, Lawrence Snyder, Harold S. Stone, Russ Tuck, and Benjamin W. Wah. Report of the Purdue Workshop on Grand Challenges in Computer Architecture for the Support of High Performance Computing. J. Parallel Distributed Comput., 16(3):199-211, 1992.
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• Shlomo Weiss and James E. Smith. A study of scalar compilation techniques for pipelined supercomputers. ACM Trans. Math. Softw., 16(3):223-245, 1990.
  Details   
• D. L. Fowler and James E. Smith. An accurate, high speed implementation of division by reciprocal approximation. In 9th Symposium on Computer Arithmetic, ARITH 1989, Santa Monica, CA, USA, September 6-8, 1989, pp. 60-67, IEEE, 1989.
  Details   
• Mark D. Hill and Alan Jay Smith. Evaluating Associativity in CPU Caches. IEEE Trans. Computers, 38(12):1612-1630, 1989.
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• James E. Smith. Dynamic Instruction Scheduling and the Astronautics ZS-1. Computer, 22(7):21-35, 1989.
  Details   
• Gurindar S. Sohi, James E. Smith, and James R. Goodman. Restricted Fetch\&Phi operations for parallel processing. In Proceedings of the 3rd international conference on Supercomputing, ICS 1989, Heraklion, Crete, Greece, June 5-9, 1989, pp. 410-416, ACM, 1989.
  Details   
• James E. Smith. Characterizing Computer Performance with a Single Number. Commun. ACM, 31(10):1202-1206, 1988.
  Details   
• James E. Smith, G. E. Dermer, B. D. Vanderwarn, S. D. Klinger, C. M. Rozewski, D. L. Fowler, K. R. Scidmore, and James Laudon. The Astronautics ZS-1 processor. In Computer Design: VLSI in Computers and Processors, ICCD 1988., Proceedings of the 1988 IEEE International Conference on, Rye Brook, NY, USA, October 3-5, 1988, pp. 307-310, IEEE, 1988.
  Details   
• James E. Smith, G. E. Dermer, B. D. Vanderwarn, S. D. Klinger, C. M. Rozewski, D. L. Fowler, K. R. Scidmore, and James Laudon. The ZS-1 Central Processor. In Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), Palo Alto, California, USA, October 5-8, 1987, pp. 199-204, ACM Press, 1987.
  Details   
• Shlomo Weiss and James E. Smith. A Study of Scalar Compilation Techniques for Pipelined Supercomputers. In Proceedings of the Second International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), Palo Alto, California, USA, October 5-8, 1987, pp. 105-109, ACM Press, 1987.
  Details   
• James E. Smith, Shlomo Weiss, and Nicholas Y. Pang. A Simulation Study of Decoupled Architecture Computers. IEEE Trans. Computers, 35(8):692-702, 1986.
  Details   
• Craig S. Holt and James E. Smith. Self-Diagnosis in Distributed Systems. IEEE Trans. Computers, 34(1):19-32, 1985.
  Details   
• James E. Smith and James R. Goodman. Instruction Cache Replacement Policies and Organizations. IEEE Trans. Computers, 34(3):234-241, 1985.
  Details   
• Mark D. Hill and Alan Jay Smith. Experimental Evaluation of On-Chip Microprocessor Cache Memories. In Proceedings of the 11th Annual Symposium on Computer Architecture, Ann Arbor, USA, June 1984, pp. 158-166, ACM, 1984.
  Details   
• James E. Smith. On Separable Unordered Codes. IEEE Trans. Computers, 33(8):741-743, 1984.
  Details   
• James E. Smith. Decoupled Access/Execute Computer Architectures. ACM Trans. Comput. Syst., 2(4):289-308, 1984.
  Details   
• Shlomo Weiss and James E. Smith. Instruction Issue Logic in Pipelined Supercomputers. IEEE Trans. Computers, 33(11):1013-1022, 1984.
  Details   
• Shlomo Weiss and James E. Smith. Instruction Issue Logic for Pipelined Supercomputers. In Proceedings of the 11th Annual Symposium on Computer Architecture, Ann Arbor, USA, June 1984, pp. 110-118, ACM, 1984.
  Details   
• James E. Smith and James R. Goodman. A Study of Instruction Cache Organizations and Replacement Policies. In Proceedings of the 10th Annual Symposium on Computer Architecture, 1983, pp. 132-137, ACM, 1983.
  Details   
• James E. Smith and Paklin Lam. A Theory of Totally Self-Checking System Design. IEEE Trans. Computers, 32(9):831-844, 1983.
  Details   
• Lionel Bening, Thomas A. Lane, Curtis R. Alexander, and James E. Smith. Developments in logic network path delay analysis. In Proceedings of the 19th Design Automation Conference, DAC '82, Las Vegas, Nevada, USA, June 14-16, 1982, pp. 605-615, ACM/IEEE, 1982.
  Details   
• James E. Smith. Decoupled access/execute computer architectures. In 9th International Symposium on Computer Architecture (ISCA 1982), Austin, TX, USA, April 26-29, 1982, pp. 112-119, IEEE Computer Society, 1982.
  Details   
• Craig S. Holt and James E. Smith. Diagnosis of Systems with Asymmetric Invalidation. IEEE Trans. Computers, 30(9):679-690, 1981.
  Details   
• James E. Smith. A Study of Branch Prediction Strategies. In Proceedings of the 8th Annual Symposium on Computer Architecture, Minneapolis, MN, USA, May 1981, pp. 135-148, IEEE Computer Society, 1981.
  Details   
• James E. Smith. Measures of the Effectiveness of Fault Signature Analysis. IEEE Trans. Computers, 29(6):510-514, 1980.
  Details   
• James E. Smith. Comments on "Redundancy Testing in Combinational Networks". IEEE Trans. Computers, 28(3):261-262, 1979.
  Details   
• James E. Smith. Universal System Diagnosis Algorithms. IEEE Trans. Computers, 28(5):374-378, 1979.
  Details   
• James E. Smith. On Necessary and Sufficient Conditions for Multiple Fault Undetectability. IEEE Trans. Computers, 28(10):801-802, 1979.
  Details   
• James E. Smith. Detection of Faults in Programmable Logic Arrays. IEEE Trans. Computers, 28(11):845-853, 1979.
  Details   
• James E. Smith and Gernot Metze. Strongly Fault Secure Logic Networks. IEEE Trans. Computers, 27(6):491-499, 1978.
  Details   
• James E. Smith. On the Existence of Combinational Logic Circuits Exhibiting Multiple Redundancy. IEEE Trans. Computers, 27(12):1221-1226, 1978.
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Sohi

• Hongil Yoon, Jason Lowe-Power, and Gurindar S. Sohi. Filtering Translation Bandwidth with Virtual Caching. In Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2018, Williamsburg, VA, USA, March 24-28, 2018, pp. 113-127, ACM, 2018.
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• Iulian Brumar, Marc Casas, Miquel Moretó, Mateo Valero, and Gurindar S. Sohi. ATM: Approximate Task Memoization in the Runtime System. In 2017 IEEE International Parallel and Distributed Processing Symposium, IPDPS 2017, Orlando, FL, USA, May 29 - June 2, 2017, pp. 1140-1150, IEEE Computer Society, 2017.
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• Hongil Yoon and Gurindar S. Sohi. Revisiting virtual L1 caches: A practical design using dynamic synonym remapping. In 2016 IEEE International Symposium on High Performance Computer Architecture, HPCA 2016, Barcelona, Spain, March 12-16, 2016, pp. 212-224, IEEE Computer Society, 2016.
  Details   
• Samuel Naffziger and Guri Sohi. Hot Chips 26 [Guest editors' introduction]. IEEE Micro, 35(2):4-5, 2015.
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• Jichuan Chang and Gurindar S. Sohi. Author retrospective for cooperative cache partitioning for chip multiprocessors. In ACM International Conference on Supercomputing 25th Anniversary Volume, pp. 80-81, ACM, 2014.
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• Gagan Gupta, Srinath Sridharan, and Gurindar S. Sohi. Globally precise-restartable execution of parallel programs. In ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI '14, Edinburgh, United Kingdom - June 09 - 11, 2014, pp. 181-192, ACM, 2014.
  Details   
• Samuel Naffziger and Guri Sohi. Welcome program chairs. In 2014 IEEE Hot Chips 26 Symposium (HCS), Cupertino, CA, USA, August 10-12, 2014, pp. 1-2, IEEE, 2014.
  Details   
• Srinath Sridharan, Gagan Gupta, and Gurindar S. Sohi. Adaptive, efficient, parallel execution of parallel programs. In ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI '14, Edinburgh, United Kingdom - June 09 - 11, 2014, pp. 169-180, ACM, 2014.
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• Srinath Sridharan, Gagan Gupta, and Gurindar S. Sohi. Holistic run-time parallelism management for time and energy efficiency. In International Conference on Supercomputing, ICS'13, Eugene, OR, USA - June 10 - 14, 2013, pp. 337-348, ACM, 2013.
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• Koushik Chakraborty, Philip M. Wells, and Gurindar S. Sohi. Supporting Overcommitted Virtual Machines through Hardware Spin Detection. IEEE Trans. Parallel Distributed Syst., 23(2):353-366, 2012.
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• Gagan Gupta and Gurindar S. Sohi. Dataflow execution of sequential imperative programs on multicore architectures. In 44rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2011, Porto Alegre, Brazil, December 3-7, 2011, pp. 59-70, ACM, 2011.
  Details   
• Matthew D. Allen, Srinath Sridharan, and Gurindar S. Sohi. Serialization sets: a dynamic dependence-based parallel execution model. In Proceedings of the 14th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, PPOPP 2009, Raleigh, NC, USA, February 14-18, 2009, pp. 85-96, ACM, 2009.
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• Gurindar S. Sohi and T. N. Vijaykumar. Speculatively Multithreaded Architectures. In Stephen W. Keckler, Kunle Olukotun, and H. Peter Hofstee, editors, Multicore Processors and Systems, Integrated Circuits and Systems, pp. 111-143, Springer, 2009.
  Details   
• Philip M. Wells, Koushik Chakraborty, and Gurindar S. Sohi. Dynamic heterogeneity and the need for multicore virtualization. ACM SIGOPS Oper. Syst. Rev., 43(2):5-14, 2009.
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• Philip M. Wells, Koushik Chakraborty, and Gurindar S. Sohi. Mixed-mode multicore reliability. In Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2009, Washington, DC, USA, March 7-11, 2009, pp. 169-180, ACM, 2009.
  Details   
• Philip M. Wells, Koushik Chakraborty, and Gurindar S. Sohi. Adapting to intermittent faults in multicore systems. In Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2008, Seattle, WA, USA, March 1-5, 2008, pp. 255-264, ACM, 2008.
  Details   
• Philip M. Wells and Gurindar S. Sohi. Serializing instructions in system-intensive workloads: Amdahl's Law strikes again. In 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 16-20 February 2008, Salt Lake City, UT, USA, pp. 264-275, IEEE Computer Society, 2008.
  Details   
• Jichuan Chang and Gurindar S. Sohi. Cooperative cache partitioning for chip multiprocessors. In Proceedings of the 21th Annual International Conference on Supercomputing, ICS 2007, Seattle, Washington, USA, June 17-21, 2007, pp. 242-252, ACM, 2007.
  Details   
• Philip M. Wells, Koushik Chakraborty, and Gurindar S. Sohi. Adapting to Intermittent Faults in Future Multicore Systems. In 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007, pp. 431, IEEE Computer Society, 2007.
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• Saisanthosh Balakrishnan and Gurindar S. Sohi. Program Demultiplexing: Data-flow based Speculative Parallelization of Methods in Sequential Programs. In 33rd International Symposium on Computer Architecture (ISCA 2006), June 17-21, 2006, Boston, MA, USA, pp. 302-313, IEEE Computer Society, 2006.
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• Koushik Chakraborty, Philip M. Wells, and Gurindar S. Sohi. Computation spreading: employing hardware migration to specialize CMP cores on-the-fly. In Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2006, San Jose, CA, USA, October 21-25, 2006, pp. 283-292, ACM, 2006.
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• Jichuan Chang and Gurindar S. Sohi. Cooperative Caching for Chip Multiprocessors. In 33rd International Symposium on Computer Architecture (ISCA 2006), June 17-21, 2006, Boston, MA, USA, pp. 264-276, IEEE Computer Society, 2006.
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• Philip M. Wells, Koushik Chakraborty, and Gurindar S. Sohi. Hardware support for spin management in overcommitted virtual machines. In 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), Seattle, Washington, USA, September 16-20, 2006, pp. 124-133, ACM, 2006.
  Details   
• J. Adam Butts and Gurindar S. Sohi. Use-Based Register Caching with Decoupled Indexing. In 31st International Symposium on Computer Architecture (ISCA 2004), 19-23 June 2004, Munich, Germany, pp. 302-313, IEEE Computer Society, 2004.
  Details   
• Allison L. Holloway and Gurindar S. Sohi. Characterization of Problem Stores. IEEE Comput. Archit. Lett., 3, 2004.
  Details   
• Jaehyuk Huh, Doug Burger, Jichuan Chang, and Gurindar S. Sohi. Speculative Incoherent Cache Protocols. IEEE Micro, 24(6):104-109, 2004.
  Details   
• Jaehyuk Huh, Jichuan Chang, Doug Burger, and Gurindar S. Sohi. Coherence decoupling: making use of incoherence. In Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2004, Boston, MA, USA, October 7-13, 2004, pp. 97-106, ACM, 2004.
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• Gurindar S. Sohi. Single-Chip Multiprocessors: The Next Wave of Computer Architecture Innovation. In 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 4-8 December 2004, Portland, OR, USA, pp. 143, IEEE Computer Society, 2004.
  Details   
• Saisanthosh Balakrishnan and Gurindar S. Sohi. Exploiting Value Locality in Physical Register Files. In Proceedings of the 36th Annual International Symposium on Microarchitecture, San Diego, CA, USA, December 3-5, 2003, pp. 265-276, IEEE Computer Society, 2003.
  Details   
• Paramjit S. Oberoi and Gurindar S. Sohi. Parallelism in the Front-End. In 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA, pp. 230-240, IEEE Computer Society, 2003.
  Details   
• J. Adam Butts and Gurindar S. Sohi. Dynamic dead-instruction detection and elimination. In Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), San Jose, California, USA, October 5-9, 2002, pp. 199-210, ACM Press, 2002.
  Details   
• J. Adam Butts and Gurindar S. Sohi. Characterizing and predicting value degree of use. In Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002, pp. 15-26, ACM/IEEE Computer Society, 2002.
  Details   
• Andreas Moshovos and Gurindar S. Sohi. Reducing Memory Latency via Read-after-Read Memory Dependence Prediction. IEEE Trans. Computers, 51(3):313-326, 2002.
  Details   
• Paramjit S. Oberoi and Gurindar S. Sohi. Out-of-Order Instruction Fetch Using Multiple Sequencers. In 31st International Conference on Parallel Processing (ICPP 2002), 20-23 August 2002, Vancouver, BC, Canada, pp. 14-26, IEEE Computer Society, 2002.
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• Amir Roth and Gurindar S. Sohi. A quantitative framework for automated pre-execution thread selection. In Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002, pp. 430-441, ACM/IEEE Computer Society, 2002.
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• Craig B. Zilles and Gurindar S. Sohi. Master/slave speculative parallelization. In Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002, pp. 85-96, ACM/IEEE Computer Society, 2002.
  Details   
• Andreas Moshovos and Gurindar S. Sohi. Microarchitectural innovations: boosting microprocessor performance beyond semiconductor technology scaling. Proc. IEEE, 89(11):1560-1575, 2001.
  Details   
• Amir Roth and Gurindar S. Sohi. Squash Reuse via a Simplified Implementation of Register Integration. J. Instr. Level Parallelism, 3, 2001.
  Details   
• Amir Roth and Gurindar S. Sohi. Speculative Data-Driven Multithreading. In Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), Nuevo Leone, Mexico, January 20-24, 2001, pp. 37-48, IEEE Computer Society, 2001.
  Details   
• Gurindar S. Sohi and Amir Roth. Speculative Multithreaded Processors. Computer, 34(4):66-71, 2001.
  Details   
• Gurindar S. Sohi. Microprocessors - 10 Years Back, 10 Years Ahead. In Informatics - 10 Years Back. 10 Years Ahead, pp. 209-218, Springer, 2001.
  Details   
• T. N. Vijaykumar, Sridhar Gopal, James E. Smith, and Gurindar S. Sohi. Speculative Versioning Cache. IEEE Trans. Parallel Distributed Syst., 12(12):1305-1317, 2001.
  Details   
• Craig B. Zilles and Gurindar S. Sohi. A Programmable Co-Processor for Profiling. In Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), Nuevo Leone, Mexico, January 20-24, 2001, pp. 241-252, IEEE Computer Society, 2001.
  Details   
• Craig B. Zilles and Gurindar S. Sohi. Execution-based prediction using speculative slices. In Proceedings of the 28th Annual International Symposium on Computer Architecture, ISCA 2001, Göteborg, Sweden, June 30-July 4, 2001, pp. 2-13, ACM, 2001.
  Details   
• J. Adam Butts and Gurindar S. Sohi. A static power model for architects. In Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 33, Monterey, California, USA, December 10-13, 2000, pp. 191-201, ACM/IEEE Computer Society, 2000.
  Details   
• Andreas Moshovos and Gurindar S. Sohi. Memory Dependence Prediction in Multimedia Applications. J. Instr. Level Parallelism, 2, 2000.
  Details   
• Andreas Moshovos and Gurindar S. Sohi. Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors. In Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, Toulouse, France, January 8-12, 2000, pp. 301-312, IEEE Computer Society, 2000.
  Details   
• Amir Roth and Gurindar S. Sohi. Register integration: a simple and efficient implementation of squash reuse. In Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 33, Monterey, California, USA, December 10-13, 2000, pp. 223-234, ACM/IEEE Computer Society, 2000.
  Details   
• Gurindar S. Sohi. Amir Roth: Speculative Multithreaded Processors. In High Performance Computing - HiPC 2000, 7th International Conference, Bangalore, India, December 17-20, 2000, Proceedings, pp. 259-270, Springer, 2000.
  Details   
• Craig B. Zilles and Gurindar S. Sohi. Understanding the backward slices of performance degrading instructions. In 27th International Symposium on Computer Architecture (ISCA 2000), June 10-14, 2000, Vancouver, BC, Canada, pp. 172-181, IEEE Computer Society, 2000.
  Details   
• Andreas Moshovos and Gurindar S. Sohi. Speculative Memory Cloaking and Bypassing. Int. J. Parallel Program., 27(6):427-456, 1999.
  Details   
• Andreas Moshovos and Gurindar S. Sohi. Read-After-Read Memory Dependence Prediction. In Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 32, Haifa, Israel, November 16-18, 1999, pp. 177-185, ACM/IEEE Computer Society, 1999.
  Details   
• Amir Roth, Andreas Moshovos, and Gurindar S. Sohi. Improving virtual function call target prediction via dependence-based pre-computation. In Proceedings of the 13th international conference on Supercomputing, ICS 1999, Rhodes, Greece, June 20-25, 1999, pp. 356-364, ACM, 1999.
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• Amir Roth and Gurindar S. Sohi. Effective Jump-Pointer Prefetching for Linked Data Structures. In Proceedings of the 26th Annual International Symposium on Computer Architecture, ISCA 1999, Atlanta, Georgia, USA, May 2-4, 1999, pp. 111-121, IEEE Computer Society, 1999.
  Details   
• T. N. Vijaykumar and Gurindar S. Sohi. Task Selection for the Multiscalar Architecture. J. Parallel Distributed Comput., 58(2):132-158, 1999.
  Details   
• Craig B. Zilles, Joel S. Emer, and Gurindar S. Sohi. The Use of Multithreading for Exception Handling. In Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 32, Haifa, Israel, November 16-18, 1999, pp. 219-229, ACM/IEEE Computer Society, 1999.
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• Sridhar Gopal, T. N. Vijaykumar, James E. Smith, and Gurindar S. Sohi. Speculative Versioning Cache. In Proceedings of the Fourth International Symposium on High-Performance Computer Architecture, Las Vegas, Nevada, USA, January 31 - February 4, 1998, pp. 195-205, IEEE Computer Society, 1998.
  Details   
• Amir Roth, Andreas Moshovos, and Gurindar S. Sohi. Dependance Based Prefetching for Linked Data Structures. In ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, USA, October 3-7, 1998, pp. 115-126, ACM Press, 1998.
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• Avinash Sodani and Gurindar S. Sohi. An Empirical Analysis of Instruction Repetition. In ASPLOS-VIII Proceedings of the 8th International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, USA, October 3-7, 1998, pp. 35-45, ACM Press, 1998.
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• Avinash Sodani and Gurindar S. Sohi. Understanding the Differences Between Value Prediction and Instruction Reuse. In Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 31, Dallas, Texas, USA, November 30 - December 2, 1998, pp. 205-215, ACM/IEEE Computer Society, 1998.
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• Gurindar S. Sohi. Retrospective: Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. In 25 Years of the International Symposia on Computer Architecture (Selected Papers), pp. 51-53, ACM, 1998.
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• Gurindar S. Sohi. Retrospective: Multiscalar Processors. In 25 Years of the International Symposia on Computer Architecture (Selected Papers), pp. 111-114, ACM, 1998.
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• Gurindar S. Sohi and Sriram Vajapeyam. Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. In 25 Years of the International Symposia on Computer Architecture (Selected Papers), pp. 329-336, ACM, 1998.
  Details   
• Gurindar S. Sohi, Scott E. Breach, and T. N. Vijaykumar. Multiscalar Processors. In 25 Years of the International Symposia on Computer Architecture (Selected Papers), pp. 521-532, ACM, 1998.
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• T. N. Vijaykumar and Gurindar S. Sohi. Task Selection for a Multiscalar Processor. In Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 31, Dallas, Texas, USA, November 30 - December 2, 1998, pp. 81-92, ACM/IEEE Computer Society, 1998.
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• Doug Burger, James R. Goodman, and Gurindar S. Sohi. Memory Systems. In Allen B. Tucker, editors, The Computer Science and Engineering Handbook, pp. 447-461, CRC Press, 1997.
  Details   
• Andreas Moshovos, Scott E. Breach, T. N. Vijaykumar, and Gurindar S. Sohi. Dynamic Speculation and Synchronization of Data Dependences. In Proceedings of the 24th International Symposium on Computer Architecture, Denver, Colorado, USA, June 2-4, 1997, pp. 181-193, ACM, 1997.
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• Andreas Moshovos and Gurindar S. Sohi. Streamlining Inter-Operation Memory Communication via Data Dependence Prediction. In Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 235-245, ACM/IEEE Computer Society, 1997.
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• Avinash Sodani and Gurindar S. Sohi. Dynamic Instruction Reuse. In Proceedings of the 24th International Symposium on Computer Architecture, Denver, Colorado, USA, June 2-4, 1997, pp. 194-205, ACM, 1997.
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• Todd M. Austin and Gurindar S. Sohi. High-Bandwidth Address Translation for Multiple-Issue Processors. In Proceedings of the 23rd Annual International Symposium on Computer Architecture, Philadelphia, PA, USA, May 22-24, 1996, pp. 158-167, ACM, 1996.
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• Manoj Franklin and Gurindar S. Sohi. ARB: A Hardware Mechanism for Dynamic Reordering of Memory References. IEEE Trans. Computers, 45(5):552-571, 1996.
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• Todd M. Austin, Dionisios N. Pnevmatikatos, and Gurindar S. Sohi. Streamlining Data Cache Access with Fast Address Calculation. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, ISCA '95, Santa Margherita Ligure, Italy, June 22-24, 1995, pp. 369-380, ACM, 1995.
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• Todd M. Austin and Gurindar S. Sohi. Zero-cycle loads: microarchitecture support for reducing load latency. In Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29 - December 1, 1995, pp. 82-92, ACM / IEEE Computer Society, 1995.
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• Gurindar S. Sohi, Scott E. Breach, and T. N. Vijaykumar. Multiscalar Processors. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, ISCA '95, Santa Margherita Ligure, Italy, June 22-24, 1995, pp. 414-425, ACM, 1995.
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• Todd M. Austin, Scott E. Breach, and Gurindar S. Sohi. Efficient Detection of All Pointer and Array Access Errors. In Proceedings of the ACM SIGPLAN'94 Conference on Programming Language Design and Implementation (PLDI), Orlando, Florida, USA, June 20-24, 1994, pp. 290-301, ACM, 1994.
  Details   
• Scott E. Breach, T. N. Vijaykumar, and Gurindar S. Sohi. The anatomy of the register file in a multiscalar processor. In Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994, pp. 181-190, ACM / IEEE Computer Society, 1994.
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• Alvin R. Lebeck and Gurindar S. Sohi. Request Combining in Multiprocessors with Arbitrary Interconnection Networks. IEEE Trans. Parallel Distributed Syst., 5(11):1140-1155, 1994.
  Details   
• Dionisios N. Pnevmatikatos and Gurindar S. Sohi. Guarded Executing and Branch Prediction in Dynamic ILP Processors. In Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, IL, USA, April 1994, pp. 120-129, IEEE Computer Society, 1994.
  Details   
• Dionisios N. Pnevmatikatos, Manoj Franklin, and Gurindar S. Sohi. Control flow prediction for dynamic ILP processors. In Proceedings of the 26th Annual International Symposium on Microarchitecture, Austin, Texas, USA, November 1993, pp. 153-163, ACM / IEEE Computer Society, 1993.
  Details   
• Gurindar S. Sohi. High-Bandwidth Interleaved Memories for Vector Processors-A Simulation Study. IEEE Trans. Computers, 42(1):34-44, 1993.
  Details   
• Todd M. Austin and Gurindar S. Sohi. Dynamic Dependency Analysis of Ordinary Programs. In Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, Australia, May 1992, pp. 342-351, ACM, 1992.
  Details   
• MenChow Chiang and Gurindar S. Sohi. Evaluating Design Choices for Shared Bus Multiprocessors in a Throughput-Oriented Environment. IEEE Trans. Computers, 41(3):297-317, 1992.
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• Manoj Franklin and Gurindar S. Sohi. The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism. In Proceedings of the 19th Annual International Symposium on Computer Architecture. Gold Coast, Australia, May 1992, pp. 58-67, ACM, 1992.
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• Manoj Franklin and Gurindar S. Sohi. Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors. In Proceedings of the 25th Annual International Symposium on Microarchitecture, Portland, Oregon, USA, November 1992, pp. 236-245, ACM / IEEE Computer Society, 1992.
  Details   
• MenChow Chiang and Gurindar S. Sohi. Experience with Mean Value Analysis Models for Evaluating Shared Bus, Throughput-Oriented Multiprocessors. In Proceedings of the 1991 ACM SIGMETRICS conference on Measurement and modeling of computer systems, San Diego, California, USA, May 21-24, 1991, pp. 90-100, ACM, 1991.
  Details   
• Gurindar S. Sohi and Manoj Franklin. High-Bandwidth Data Memory Systems for Superscalar Processors. In ASPLOS-IV Proceedings - Forth International Conference on Architectural Support for Programming Languages and Operating Systems, Santa Clara, California, USA, April 8-11, 1991, pp. 53-62, ACM Press, 1991.
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• Sriram Vajapeyam, Gurindar S. Sohi, and Wei-Chung Hsu. An Empirical Study of the CRAY Y-MP Processor Using the Perfect Club Benchmarks. In Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, Canada, May, 27-30 1991, pp. 170-179, ACM, 1991.
  Details   
• Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, and Dhiraj K. Pradhan. Design and Analysis of a Gracefully Degrading Interleaved Memory System. IEEE Trans. Computers, 39(1):63-71, 1990.
  Details   
• Steven L. Scott and Gurindar S. Sohi. The Use of Feedback in Multiprocessors and Its Application to Tree Saturation Control. IEEE Trans. Parallel Distributed Syst., 1(4):385-398, 1990.
  Details   
• Gurindar S. Sohi. Instruction Issue Logic for High-Performance Interruptible, Multiple Functional Unit, Pipelines Computers. IEEE Trans. Computers, 39(3):349-359, 1990.
  Details   
• Gurindar S. Sohi and Wei-Chung Hsu. The use of intermediate memories for low-latency memory access in supercomputer scalar units. J. Supercomput., 4(1):5-21, 1990.
  Details   
• Shreekant S. Thakkar, Michel Dubois, Anthony T. Laundrie, Gurindar S. Sohi, David V. James, Stein Gjessing, Manu Thapar, Bruce Delagi, Michael J. Carlton, and Alvin M. Despain. Scalable Shared-Memory Multiprocessor Architectures. Computer, 23(6):71-83, 1990.
  Details   
• Sriram Vajapeyam, Gurindar S. Sohi, and Wei-Chung Hsu. Exploitation of operation-level parallelism in a processor of the CRAY X-MP. In Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1990, Cambridge, MA, USA, 17-19 September, 1990, pp. 20-23, IEEE Computer Society, 1990.
  Details   
• V. S. Madan, C.-J. Peng, and Gurindar S. Sohi. On the Adequacy of Direct Mapped Caches for Lisp and Prolog Data Reference Patterns. In Logic Programming, Proceedings of the North American Conference 1989, Cleveland, Ohio, USA, October 16-20, 1989. 2 Volumes, pp. 888-906, MIT Press, 1989.
  Details   
• Steven L. Scott and Gurindar S. Sohi. Using Feedback to Control Tree Saturation in Multistage Interconnection Networks. In Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, Israel, June 1989, pp. 167-176, ACM, 1989.
  Details   
• Gurindar S. Sohi. Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors. IEEE Trans. Computers, 38(4):484-492, 1989.
  Details   
• Gurindar S. Sohi and Sriram Vajapeyam. Tradeoffs in Instruction Format Design for Horizontal Architectures. In ASPLOS-III Proceedings - Third International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, USA, April 3-6, 1989, pp. 15-25, ACM Press, 1989.
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• Gurindar S. Sohi, Manoj Franklin, and Kewal K. Saluja. A study of time-redundant fault tolerance techniques for high-performance pipelined computers. In Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, FTCS 1989, Chicago, IL, USA, 21-23 June, 1989, pp. 436-443, IEEE Computer Society, 1989.
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• Gurindar S. Sohi, James E. Smith, and James R. Goodman. Restricted Fetch\&Phi operations for parallel processing. In Proceedings of the 3rd international conference on Supercomputing, ICS 1989, Heraklion, Crete, Greece, June 5-9, 1989, pp. 410-416, ACM, 1989.
  Details   
• Mary K. Vernon, Rajeev Jog, and Gurindar S. Sohi. Performance Analysis of Hierarchical Cache-Consistent Multiprocessors. Perform. Evaluation, 9(4):287-302, 1989.
  Details   
• Andrew R. Pleszkun and Gurindar S. Sohi. The Performance Potential of Multiple Functional Unit Processors. In Proceedings of the 15th Annual International Symposium on Computer Architecture, Honolulu, Hawaii, USA, May-June 1988, pp. 37-44, IEEE Computer Society, 1988.
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• Andrew R. Pleszkun and Gurindar S. Sohi. Multiple instruction issue and single-chip processors. In Proceedings of the 21st Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1988, San Diego, California, USA, November 28 - December 2, 1988, pp. 64-66, ACM/IEEE, 1988.
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• Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, and Dhiraj K. Pradhan. Organization and Analysis of a Gracefully-Degrading Interleaved Memory System. In Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh, PA, USA, June 1987, pp. 224-231, 1987.
  Details   
• Gurindar S. Sohi and Sriram Vajapeyam. Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. In Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh, PA, USA, June 1987, pp. 27-34, 1987.
  Details   
• Andrew R. Pleszkun, Gurindar S. Sohi, Bassam Z. Kahhaleh, and Edward S. Davidson. Features of the Structured Memory Access (SMA) Architecture. In Spring COMPCON'86, Digest of Papers, Thirty-First IEEE Computer Society International Conference, San Francisco, California, USA, March 3-6, 1986, pp. 259-265, IEEE Computer Society, 1986.
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• Gurindar S. Sohi, Edward S. Davidson, and Janak H. Patel. An Efficient LISP-Execution Architecture with a New Representation for List Structures. In Proceedings of the 12th Annual Symposium on Computer Architecture, Boston, MA, USA, June 1985, pp. 91-98, IEEE Computer Society, 1985.
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Tannu

• Ramin Ayanzadeh, Poulami Das, Swamit S. Tannu, and Moinuddin K. Qureshi. EQUAL: Improving the Fidelity of Quantum Annealers by Injecting Controlled Perturbations. CoRR, abs/2108.10964, 2021.
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• Moinuddin K. Qureshi and Swamit S. Tannu. Quantum Computing and the Design of the Ultimate Accelerator. IEEE Micro, 41(5):8-14, 2021.
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• Salonik Resch, Swamit S. Tannu, Ulya R. Karpuzcu, and Moinuddin K. Qureshi. A Day In the Life of a Quantum Error. IEEE Comput. Archit. Lett., 20(1):13-16, 2021.
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• Salonik Resch, Anthony Gutierrez, Joon Suk Huh, Srikant Bharadwaj, Yasuko Eckert, Gabriel H. Loh, Mark Oskin, and Swamit S. Tannu. Accelerating Variational Quantum Algorithms Using Circuit Concurrency. CoRR, abs/2109.01714, 2021.
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• Poulami Das, Swamit S. Tannu, Prashant J. Nair, and Moinuddin K. Qureshi. A Case for Multi-Programming Quantum Computers. In Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2019, Columbus, OH, USA, October 12-16, 2019, pp. 291-303, ACM, 2019.
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• Swamit S. Tannu and Moinuddin K. Qureshi. Not All Qubits Are Created Equal: A Case for Variability-Aware Policies for NISQ-Era Quantum Computers. In Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2019, Providence, RI, USA, April 13-17, 2019, pp. 987-999, ACM, 2019.
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• Swamit S. Tannu, Poulami Das, Michael L. Lewis, Robert F. Krick, Douglas M. Carmean, and Moinuddin K. Qureshi. A case for superconducting accelerators. In Proceedings of the 16th ACM International Conference on Computing Frontiers, CF 2019, Alghero, Italy, April 30 - May 2, 2019, pp. 67-75, ACM, 2019.
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• Swamit S. Tannu and Moinuddin K. Qureshi. Ensemble of Diverse Mappings: Improving Reliability of Quantum Computers by Orchestrating Dissimilar Mistakes. In Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2019, Columbus, OH, USA, October 12-16, 2019, pp. 253-265, ACM, 2019.
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• Swamit S. Tannu and Moinuddin K. Qureshi. Mitigating Measurement Errors in Quantum Computers by Exploiting State-Dependent Bias. In Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2019, Columbus, OH, USA, October 12-16, 2019, pp. 279-290, ACM, 2019.
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• Swamit S. Tannu, Poulami Das, Michael L. Lewis, Robert F. Krick, Douglas M. Carmean, and Moinuddin K. Qureshi. A Case for Superconducting Accelerators. CoRR, abs/1902.04641, 2019.
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• Swamit S. Tannu and Moinuddin K. Qureshi. A Case for Variability-Aware Policies for NISQ-Era Quantum Computers. CoRR, abs/1805.10224, 2018.
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• Swamit S. Tannu, Douglas M. Carmean, and Moinuddin K. Qureshi. Cryogenic-DRAM based memory system for scalable quantum computers: a feasibility study. In Proceedings of the International Symposium on Memory Systems, MEMSYS 2017, Alexandria, VA, USA, October 02 - 05, 2017, pp. 189-195, ACM, 2017.
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• Swamit S. Tannu, Zachary A. Myers, Prashant J. Nair, Douglas M. Carmean, and Moinuddin K. Qureshi. Taming the instruction bandwidth of quantum computers via hardware-managed error correction. In Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2017, Cambridge, MA, USA, October 14-18, 2017, pp. 679-691, ACM, 2017.
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Wood

• Alexandru Dutu, Matthew D. Sinclair, Bradford M. Beckmann, David A. Wood, and Marcus Chow. Independent Forward Progress of Work-groups. In 47th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2020, Valencia, Spain, May 30 - June 3, 2020, pp. 1022-1035, IEEE, 2020.
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• Jason Lowe-Power, Abdul Mutaal Ahmad, Ayaz Akram, Mohammad Alian, Rico Amslinger, Matteo Andreozzi, Adrià Armejach, Nils Asmussen, Srikant Bharadwaj, Gabe Black, Gedare Bloom, Bobby R. Bruce, Daniel Rodrigues Carvalho, Jerónimo Castrillón, Lizhong Chen, Nicolas Derumigny, Stephan Diestelhorst, Wendy Elsasser, Marjan Fariborz, Amin Farmahini Farahani, Pouya Fotouhi, Ryan Gambord, Jayneel Gandhi, Dibakar Gope, Thomas Grass, Bagus Hanindhito, Andreas Hansson, Swapnil Haria, Austin Harris, Timothy Hayes, Adrian Herrera, Matthew Horsnell, Syed Ali Raza Jafri, Radhika Jagtap, Hanhwi Jang, Reiley Jeyapaul, Timothy M. Jones, Matthias Jung, Subash Kannoth, Hamidreza Khaleghzadeh, Yuetsu Kodama, Tushar Krishna, Tommaso Marinelli, Christian Menard, Andrea Mondelli, Tiago Mück, Omar Naji, Krishnendra Nathella, Hoa Nguyen, Nikos Nikoleris, Lena E. Olson, Marc S. Orr, Binh Pham, Pablo Prieto, Trivikram Reddy, Alec Roelke, Mahyar Samani, Andreas Sandberg, Javier Setoain, Boris Shingarov, Matthew D. Sinclair, Tuan Ta, Rahul Thakur, Giacomo Travaglini, Michael Upton, Nilay Vaish, Ilias Vougioukas, Zhengrong Wang, Norbert Wehn, Christian Weis, David A. Wood, Hongil Yoon, and Éder F. Zulian. The gem5 Simulator: Version 20.0+. CoRR, abs/2007.03152, 2020.
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• Vijay Nagarajan, Daniel J. Sorin, Mark D. Hill, and David A. Wood. A Primer on Memory Consistency and Cache Coherence, Second Edition, Synthesis Lectures on Computer Architecture, Morgan \& Claypool Publishers, 2020.
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• Muhammad Shoaib Bin Altaf and David A. Wood. LogCA: A High-Level Performance Model for Hardware Accelerators. In Proceedings of the 44th Annual International Symposium on Computer Architecture, ISCA 2017, Toronto, ON, Canada, June 24-28, 2017, pp. 375-388, ACM, 2017.
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• Lena E. Olson, Mark D. Hill, and David A. Wood. Crossing Guard: Mediating Host-Accelerator Coherence Interactions. In Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2017, Xi'an, China, April 8-12, 2017, pp. 163-176, ACM, 2017.
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• Marc S. Orr, Shuai Che, Bradford M. Beckmann, Mark Oskin, Steven K. Reinhardt, and David A. Wood. Gravel: fine-grain GPU-initiated network messages. In Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2017, Denver, CO, USA, November 12 - 17, 2017, pp. 23:1-23:12, ACM, 2017.
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• Somayeh Sardashti and David A. Wood. Could Compression Be of General Use? Evaluating Memory Compression across Domains. ACM Trans. Archit. Code Optim., 14(4):44:1-44:24, 2017.
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• Rathijit Sen and David A. Wood. Energy-Proportional Computing: A New Definition. Computer, 50(8):26-33, 2017.
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• Rathijit Sen and David A. Wood. Pareto Governors for Energy-Optimal Computing. ACM Trans. Archit. Code Optim., 14(1):6:1-6:25, 2017.
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• Johnathan Alsop, Marc S. Orr, Bradford M. Beckmann, and David A. Wood. Lazy release consistency for GPUs. In 49th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2016, Taipei, Taiwan, October 15-19, 2016, pp. 26:1-26:13, IEEE Computer Society, 2016.
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• Mark D. Hill, Sarita V. Adve, Luis Ceze, Mary Jane Irwin, David R. Kaeli, Margaret Martonosi, Josep Torrellas, Thomas F. Wenisch, David A. Wood, and Katherine A. Yelick. 21st Century Computer Architecture. CoRR, abs/1609.06756, 2016.
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• Jason Lowe-Power, Mark D. Hill, and David A. Wood. When to use 3D Die-Stacked Memory for Bandwidth-Constrained Big Data Workloads. CoRR, abs/1608.07485, 2016.
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• Somayeh Sardashti, André Seznec, and David A. Wood. Yet Another Compressed Cache: A Low-Cost Yet Effective Compressed Cache. ACM Trans. Archit. Code Optim., 13(3):27:1-27:25, 2016.
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• Rathijit Sen and David A. Wood. GPGPU Footprint Models to Estimate per-Core Power. IEEE Comput. Archit. Lett., 15(2):97-100, 2016.
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• Nilay Vaish, Michael C. Ferris, and David A. Wood. Optimization Models for Three On-Chip Network Problems. ACM Trans. Archit. Code Optim., 13(3):26:1-26:27, 2016.
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• Muhammad Shoaib Bin Altaf and David A. Wood. LogCA: A Performance Model for Hardware Accelerators. IEEE Comput. Archit. Lett., 14(2):132-135, 2015.
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• Joel Hestness, Stephen W. Keckler, and David A. Wood. GPU Computing Pipeline Inefficiencies and Optimization Opportunities in Heterogeneous CPU-GPU Processors. In 2015 IEEE International Symposium on Workload Characterization, IISWC 2015, Atlanta, GA, USA, October 4-6, 2015, pp. 87-97, IEEE Computer Society, 2015.
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• Lena E. Olson, Jason Power, Mark D. Hill, and David A. Wood. Border control: sandboxing accelerators. In Proceedings of the 48th International Symposium on Microarchitecture, MICRO 2015, Waikiki, HI, USA, December 5-9, 2015, pp. 470-481, ACM, 2015.
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• Marc S. Orr, Shuai Che, Ayse Yilmazer, Bradford M. Beckmann, Mark D. Hill, and David A. Wood. Synchronization Using Remote-Scope Promotion. In Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2015, Istanbul, Turkey, March 14-18, 2015, pp. 73-86, ACM, 2015.
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• Jason Power, Joel Hestness, Marc S. Orr, Mark D. Hill, and David A. Wood. gem5-gpu: A Heterogeneous CPU-GPU Simulator. IEEE Comput. Archit. Lett., 14(1):34-36, 2015.
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• Jason Power, Yinan Li, Mark D. Hill, Jignesh M. Patel, and David A. Wood. Implications of Emerging 3D GPU Architecture on the Scan Primitive. SIGMOD Rec., 44(1):18-23, 2015.
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• Jason Power, Yinan Li, Mark D. Hill, Jignesh M. Patel, and David A. Wood. Toward GPUs being mainstream in analytic processing: An initial argument using simple scan-aggregate queries. In Proceedings of the 11th International Workshop on Data Management on New Hardware, DaMoN 2015, Melbourne, VIC, Australia, May 31 - June 04, 2015, pp. 11:1-11:8, ACM, 2015.
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• Somayeh Sardashti, Angelos Arelakis, Per Stenström, and David A. Wood. A Primer on Compression in the Memory Hierarchy, Synthesis Lectures on Computer Architecture, Morgan \& Claypool Publishers, 2015.
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• Blake A. Hechtman, Shuai Che, Derek R. Hower, Yingying Tian, Bradford M. Beckmann, Mark D. Hill, Steven K. Reinhardt, and David A. Wood. QuickRelease: A throughput-oriented approach to release consistency on GPUs. In 20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014, Orlando, FL, USA, February 15-19, 2014, pp. 189-200, IEEE Computer Society, 2014.
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• Joel Hestness, Stephen W. Keckler, and David A. Wood. A comparative analysis of microarchitecture effects on CPU and GPU memory system behavior. In 2014 IEEE International Symposium on Workload Characterization, IISWC 2014, Raleigh, NC, USA, October 26-28, 2014, pp. 150-160, IEEE Computer Society, 2014.
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• Derek R. Hower, Blake A. Hechtman, Bradford M. Beckmann, Benedict R. Gaster, Mark D. Hill, Steven K. Reinhardt, and David A. Wood. Heterogeneous-race-free memory models. In Architectural Support for Programming Languages and Operating Systems, ASPLOS 2014, Salt Lake City, UT, USA, March 1-5, 2014, pp. 427-440, ACM, 2014.
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• Marc S. Orr, Bradford M. Beckmann, Steven K. Reinhardt, and David A. Wood. Fine-grain task aggregation and coordination on GPUs. In ACM/IEEE 41st International Symposium on Computer Architecture, ISCA 2014, Minneapolis, MN, USA, June 14-18, 2014, pp. 181-192, IEEE Computer Society, 2014.
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• Jason Power, Mark D. Hill, and David A. Wood. Supporting x86-64 address translation for 100s of GPU lanes. In 20th IEEE International Symposium on High Performance Computer Architecture, HPCA 2014, Orlando, FL, USA, February 15-19, 2014, pp. 568-578, IEEE Computer Society, 2014.
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• Somayeh Sardashti and David A. Wood. Decoupled Compressed Cache: Exploiting Spatial Locality for Energy Optimization. IEEE Micro, 34(3):91-99, 2014.
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• Somayeh Sardashti, André Seznec, and David A. Wood. Skewed Compressed Caches. In 47th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2014, Cambridge, United Kingdom, December 13-17, 2014, pp. 331-342, IEEE Computer Society, 2014.
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• David A. Wood. Resolved: specialized architectures, languages, and system software should supplant general-purpose alternatives within a decade. In Architectural Support for Programming Languages and Operating Systems, ASPLOS 2014, Salt Lake City, UT, USA, March 1-5, 2014, pp. 653-654, ACM, 2014.
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• Tony Nowatzki, Michael C. Ferris, Karu Sankaralingam, Cristian Estan, Nilay Vaish, and David A. Wood. Optimization and Mathematical Modeling in Computer Architecture, Synthesis Lectures on Computer Architecture, Morgan \& Claypool Publishers, 2013.
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• Jason Power, Arkaprava Basu, Junli Gu, Sooraj Puthoor, Bradford M. Beckmann, Mark D. Hill, Steven K. Reinhardt, and David A. Wood. Heterogeneous system coherence for integrated CPU-GPU systems. In The 46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-46, Davis, CA, USA, December 7-11, 2013, pp. 457-467, ACM, 2013.
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• Somayeh Sardashti and David A. Wood. Decoupled compressed cache: exploiting spatial locality for energy-optimized compressed caching. In The 46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-46, Davis, CA, USA, December 7-11, 2013, pp. 62-73, ACM, 2013.
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• Rathijit Sen and David A. Wood. Reuse-based online models for caches. In ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS '13, Pittsburgh, PA, USA, June 17-21, 2013, pp. 279-292, ACM, 2013.
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• Yasuko Eckert, Srilatha Manne, Michael J. Schulte, and David A. Wood. Something old and something new: P-states can borrow microarchitecture techniques too. In International Symposium on Low Power Electronics and Design, ISLPED'12, Redondo Beach, CA, USA - July 30 - August 01, 2012, pp. 385-390, ACM, 2012.
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• Somayeh Sardashti and David A. Wood. UniFI: leveraging non-volatile memories for a unified fault tolerance and idle power management technique. In International Conference on Supercomputing, ICS'12, Venice, Italy, June 25-29, 2012, pp. 59-68, ACM, 2012.
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• Nathan L. Binkert, Bradford M. Beckmann, Gabriel Black, Steven K. Reinhardt, Ali G. Saidi, Arkaprava Basu, Joel Hestness, Derek Hower, Tushar Krishna, Somayeh Sardashti, Rathijit Sen, Korey Sewell, Muhammad Shoaib Bin Altaf, Nilay Vaish, Mark D. Hill, and David A. Wood. The gem5 simulator. SIGARCH Comput. Archit. News, 39(2):1-7, 2011.
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• Jayaram Bobba, Marc Lupon, Mark D. Hill, and David A. Wood. Safe and efficient supervised memory systems. In 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), February 12-16 2011, San Antonio, Texas, USA, pp. 369-380, IEEE Computer Society, 2011.
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• Derek Hower, Polina Dudnik, Mark D. Hill, and David A. Wood. Calvin: Deterministic or not? Free will to choose. In 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), February 12-16 2011, San Antonio, Texas, USA, pp. 333-334, IEEE Computer Society, 2011.
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• Daniel J. Sorin, Mark D. Hill, and David A. Wood. A Primer on Memory Consistency and Cache Coherence, Synthesis Lectures on Computer Architecture, Morgan \& Claypool Publishers, 2011.
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• Dan Gibson and David A. Wood. Forwardflow: a scalable core for power-constrained CMPs. In 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 14-25, ACM, 2010.
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• Yasuko Watanabe, John D. Davis, and David A. Wood. WiDGET: Wisconsin decoupled grid execution tiles. In 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 2-13, ACM, 2010.
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• Jayaram Bobba, Weiwei Xiong, Luke Yen, Mark D. Hill, and David A. Wood. StealthTest: Low Overhead Online Software Testing Using Transactional Memory. In PACT 2009, Proceedings of the 18th International Conference on Parallel Architectures and Compilation Techniques, 12-16 September 2009, Raleigh, North Carolina, USA, pp. 146-155, IEEE Computer Society, 2009.
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• Jayaram Bobba, Kevin E. Moore, Haris Volos, Luke Yen, Mark D. Hill, Michael M. Swift, and David A. Wood. Performance Pathologies in Hardware Transactional Memory. IEEE Micro, 28(1):32-41, 2008.
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• Jayaram Bobba, Neelam Goyal, Mark D. Hill, Michael M. Swift, and David A. Wood. TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory. In 35th International Symposium on Computer Architecture (ISCA 2008), June 21-25, 2008, Beijing, China, pp. 127-138, IEEE Computer Society, 2008.
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• Alaa R. Alameldeen and David A. Wood. Interactions Between Compression and Prefetching in Chip Multiprocessors. In 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 10-14 February 2007, Phoenix, Arizona, USA, pp. 228-239, IEEE Computer Society, 2007.
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• Jayaram Bobba, Kevin E. Moore, Haris Volos, Luke Yen, Mark D. Hill, Michael M. Swift, and David A. Wood. Performance pathologies in hardware transactional memory. In 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 81-91, ACM, 2007.
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• Mark D. Hill, Derek Hower, Kevin E. Moore, Michael M. Swift, Haris Volos, and David A. Wood. A Case for Deconstructing Hardware Transactional Memory Systems. In Programming Models for Ubiquitous Parallelism, 02.09. - 07.09.2007, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany, 2007.
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• Luke Yen, Jayaram Bobba, Michael R. Marty, Kevin E. Moore, Haris Volos, Mark D. Hill, Michael M. Swift, and David A. Wood. LogTM-SE: Decoupling Hardware Transactional Memory from Caches. In 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 10-14 February 2007, Phoenix, Arizona, USA, pp. 261-272, IEEE Computer Society, 2007.
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• Alaa R. Alameldeen and David A. Wood. IPC Considered Harmful for Multiprocessor Workloads. IEEE Micro, 26(4):8-17, 2006.
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• Bradford M. Beckmann, Michael R. Marty, and David A. Wood. ASR: Adaptive Selective Replication for CMP Caches. In 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 9-13 December 2006, Orlando, Florida, USA, pp. 443-454, IEEE Computer Society, 2006.
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• Kevin E. Moore, Jayaram Bobba, Michelle J. Moravan, Mark D. Hill, and David A. Wood. LogTM: log-based transactional memory. In 12th International Symposium on High-Performance Computer Architecture, HPCA-12 2006, Austin, Texas, USA, February 11-15, 2006, pp. 254-265, IEEE Computer Society, 2006.
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• Michelle J. Moravan, Jayaram Bobba, Kevin E. Moore, Luke Yen, Mark D. Hill, Ben Liblit, Michael M. Swift, and David A. Wood. Supporting nested transactional memory in logTM. In Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2006, San Jose, CA, USA, October 21-25, 2006, pp. 359-370, ACM, 2006.
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• David A. Wood. Keynote talk challenges in chip multiprocessor memory systems. In Proceedings of the 2006 workshop on Memory System Performance and Correctness, San Jose, California, USA, October 11, 2006, pp. 61, ACM, 2006.
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• Babak Falsafi and David A. Wood. Evaluating scheduling policies for fine-grain communication protocols on a cluster of SMPs. J. Parallel Distributed Comput., 65(4):464-478, 2005.
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• Martin Karlsson, Erik Hagersten, Kevin E. Moore, and David A. Wood. Exploring Processor Design Options for Java-Based Middleware. In 34th International Conference on Parallel Processing (ICPP 2005), 14-17 June 2005, Oslo, Norway, pp. 59-68, IEEE Computer Society, 2005.
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• Milo M. K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, and David A. Wood. Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset. SIGARCH Comput. Archit. News, 33(4):92-99, 2005.
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• Michael R. Marty, Jesse D. Bingham, Mark D. Hill, Alan J. Hu, Milo M. K. Martin, and David A. Wood. Improving Multiple-CMP Systems Using Token Coherence. In 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 12-16 February 2005, San Francisco, CA, USA, pp. 328-339, IEEE Computer Society, 2005.
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• Alaa R. Alameldeen and David A. Wood. Adaptive Cache Compression for High-Performance Processors. In 31st International Symposium on Computer Architecture (ISCA 2004), 19-23 June 2004, Munich, Germany, pp. 212-223, IEEE Computer Society, 2004.
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• Bradford M. Beckmann and David A. Wood. Managing Wire Delay in Large Chip-Multiprocessor Caches. In 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 4-8 December 2004, Portland, OR, USA, pp. 319-330, IEEE Computer Society, 2004.
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• Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, and David A. Wood. Using Speculation to Simplify Multiprocessor Design. In 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, IEEE Computer Society, 2004.
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• Alaa R. Alameldeen, Milo M. K. Martin, Carl J. Mauer, Kevin E. Moore, Min Xu, Mark D. Hill, David A. Wood, and Daniel J. Sorin. Simulating a \textdollar2M Commercial Server on a \textdollar2K PC. Computer, 36(2):50-57, 2003.
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• Alaa R. Alameldeen and David A. Wood. Addressing Workload Variability in Architectural Simulations. IEEE Micro, 23(6):94-98, 2003.
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• Alaa R. Alameldeen and David A. Wood. Variability in Architectural Simulations of Multi-Threaded Workloads. In Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), Anaheim, California, USA, February 8-12, 2003, pp. 7-18, IEEE Computer Society, 2003.
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• Bradford M. Beckmann and David A. Wood. TLC: Transmission Line Caches. In Proceedings of the 36th Annual International Symposium on Microarchitecture, San Diego, CA, USA, December 3-5, 2003, pp. 43-54, IEEE Computer Society, 2003.
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• Martin Karlsson, Kevin E. Moore, Erik Hagersten, and David A. Wood. Memory System Behavior of Java-Based Middleware. In Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), Anaheim, California, USA, February 8-12, 2003, pp. 217-228, IEEE Computer Society, 2003.
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• Milo M. K. Martin, Mark D. Hill, and David A. Wood. Token Coherence: A New Framework for Shared-Memory Multiprocessors. IEEE Micro, 23(6):108-116, 2003.
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• Milo M. K. Martin, Mark D. Hill, and David A. Wood. Token Coherence: Decoupling Performance and Correctness. In 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA, pp. 182-193, IEEE Computer Society, 2003.
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• Milo M. K. Martin, Pacia J. Harper, Daniel J. Sorin, Mark D. Hill, and David A. Wood. Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors. In 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA, pp. 206-217, IEEE Computer Society, 2003.
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• Daniel J. Sorin, Mark D. Hill, and David A. Wood. Dynamic Verification of End-to-End Multiprocessor Invariants. In 2003 International Conference on Dependable Systems and Networks (DSN 2003), 22-25 June 2003, San Francisco, CA, USA, Proceedings, pp. 281-290, IEEE Computer Society, 2003.
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• Ragu Athinarayanan, Mohammad R. Sayeh, and David A. Wood. Adaptive competitive self-organizing associative memory. IEEE Trans. Syst. Man Cybern. Part A, 32(4):461-471, 2002.
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• Milo M. K. Martin, Daniel J. Sorin, Mark D. Hill, and David A. Wood. Bandwidth Adaptive Snooping. In Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), Boston, Massachusettes, USA, February 2-6, 2002, pp. 251-262, IEEE Computer Society, 2002.
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• Carl J. Mauer, Mark D. Hill, and David A. Wood. Full-system timing-first simulation. In Proceedings of the International Conference on Measurements and Modeling of Computer Systems, SIGMETRICS 2002, June 15-19, 2002, Marina Del Rey, California, USA, pp. 108-116, ACM, 2002.
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• Daniel J. Sorin, Manoj Plakal, Anne Condon, Mark D. Hill, Milo M. K. Martin, and David A. Wood. Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol. IEEE Trans. Parallel Distributed Syst., 13(6):556-578, 2002.
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• Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, and David A. Wood. SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery. In 29th International Symposium on Computer Architecture (ISCA 2002), 25-29 May 2002, Anchorage, AK, USA, pp. 123-134, IEEE Computer Society, 2002.
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• Milo M. K. Martin, Daniel J. Sorin, Anastassia Ailamaki, Alaa R. Alameldeen, Ross M. Dickson, Carl J. Mauer, Kevin E. Moore, Manoj Plakal, Mark D. Hill, and David A. Wood. Timestamp snooping: an approach for extending SMPs. In ASPLOS-IX Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, MA, USA, November 12-15, 2000, pp. 25-36, ACM Press, 2000.
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• Shubhendu S. Mukherjee, Steven K. Reinhardt, Babak Falsafi, Mike Litzkow, Mark D. Hill, David A. Wood, Steven Huss-Lederman, and James R. Larus. Wisconsin Wind Tunnel II: a fast, portable parallel architecture simulator. IEEE Concurr., 8(4):12-20, 2000.
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• Anastassia Ailamaki, David J. DeWitt, Mark D. Hill, and David A. Wood. DBMSs on a Modern Processor: Where Does Time Go?. In VLDB'99, Proceedings of 25th International Conference on Very Large Data Bases, September 7-10, 1999, Edinburgh, Scotland, UK, pp. 266-277, Morgan Kaufmann, 1999.
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• E. Ender Bilir, Ross M. Dickson, Ying Hu, Manoj Plakal, Daniel J. Sorin, Mark D. Hill, and David A. Wood. Multicast Snooping: A New Coherence Method Using a Multicast Address Network. In Proceedings of the 26th Annual International Symposium on Computer Architecture, ISCA 1999, Atlanta, Georgia, USA, May 2-4, 1999, pp. 294-304, IEEE Computer Society, 1999.
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• Babak Falsafi and David A. Wood. Parallel Dispatch Queue: A Queue-Based Programming Abstraction to Parallelize Fine-Grain Communication Protocols. In Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, Orlando, FL, USA, January 9-12, 1999, pp. 182-192, IEEE Computer Society, 1999.
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• Steven K. Reinhardt, Robert W. Pfile, and David A. Wood. Hardware Support for Flexible Distributed Shared Memory. IEEE Trans. Computers, 47(10):1056-1072, 1998.
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• Steven K. Reinhardt, James R. Larus, and David A. Wood. Retrospective: Tempest and Typhoon: User-Level Shared Memory. In 25 Years of the International Symposia on Computer Architecture (Selected Papers), pp. 98-102, ACM, 1998.
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• Steven K. Reinhardt, James R. Larus, and David A. Wood. Tempest and Typhoon: User-Level Shared Memory. In 25 Years of the International Symposia on Computer Architecture (Selected Papers), pp. 497-508, ACM, 1998.
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• Ioannis Schoinas, Babak Falsafi, Mark D. Hill, James R. Larus, and David A. Wood. Sirocco: Cost-Effective Fine-Grain Distributed Shared Memory. In Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, Paris, France, October 12-18, 1998, pp. 40, IEEE Computer Society, 1998.
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• Daniel J. Sorin, Vijay S. Pai, Sarita V. Adve, Mary K. Vernon, and David A. Wood. Analytic Evaluation of Shared-memory Systems with ILP Processors. In Proceedings of the 25th Annual International Symposium on Computer Architecture, ISCA 1998, Barcelona, Spain, June 27 - July 1, 1998, pp. 380-391, IEEE Computer Society, 1998.
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• Babak Falsafi and David A. Wood. Modeling Cost/Performance of a Parallel Computer Simulator. ACM Trans. Model. Comput. Simul., 7(1):104-130, 1997.
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• Babak Falsafi and David A. Wood. Scheduling Communication on a SMP Node Parallel Machine. In Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), San Antonio, Texas, USA, February 1-5, 1997, pp. 128-138, IEEE Computer Society, 1997.
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• Babak Falsafi and David A. Wood. Reactive NUMA: A Design for Unifying S-COMA and CC-NUMA. In Proceedings of the 24th International Symposium on Computer Architecture, Denver, Colorado, USA, June 2-4, 1997, pp. 229-240, ACM, 1997.
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• Alvin R. Lebeck and David A. Wood. Active Memory: A New Abstraction for Memory System Simulation. ACM Trans. Model. Comput. Simul., 7(1):42-77, 1997.
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• Yuanyuan Zhou, Liviu Iftode, Jaswinder Pal Singh, Kai Li, Brian R. Toonen, Ioannis Schoinas, Mark D. Hill, and David A. Wood. Relaxed Consistency and Coherence Granularity in DSM Systems: A Performance Evaluation. In Proceedings of the Sixth ACM SIGPLAN Symposium on Principles \& Practice of Parallel Programming (PPOPP), Las Vegas, Nevada, USA, June 18-21, 1997, pp. 193-205, ACM, 1997.
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• Doug Burger, Rahmat S. Hyder, Barton P. Miller, and David A. Wood. Paging tradeoffs in distributed-shared-memory multiprocessors. J. Supercomput., 10(1):87-104, 1996.
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• Rahmat S. Hyder and David A. Wood. Synchronization Hardware for Networks of Workstations: Performance vs. Cost. In Proceedings of the 10th international conference on Supercomputing, ICS 1996, Philadelphia, PA, USA, May 25-28, 1996, pp. 245-252, ACM, 1996.
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• Shubhendu S. Mukherjee, Babak Falsafi, Mark D. Hill, and David A. Wood. Coherent Network Interfaces for Fine-Grain Communication. In Proceedings of the 23rd Annual International Symposium on Computer Architecture, Philadelphia, PA, USA, May 22-24, 1996, pp. 247-258, ACM, 1996.
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• Steven K. Reinhardt, Robert W. Pfile, and David A. Wood. Decoupled Hardware Support for Distributed Shared Memory. In Proceedings of the 23rd Annual International Symposium on Computer Architecture, Philadelphia, PA, USA, May 22-24, 1996, pp. 34-43, ACM, 1996.
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• David A. Wood. Problems, Challenges and the Importance of Performance Evaluation. ACM Comput. Surv., 28(4es):36, 1996.
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• David A. Wood, Mark D. Hill, and James R. Larus. The Tempest approach to distributed shared memory. In 1996 International Conference on Computer Design (ICCD '96), VLSI in Computers and Processors, October 7-9, 1996, Austin, TX, USA, Proceedings, pp. 63-64, IEEE Computer Society, 1996.
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• Doug Burger and David A. Wood. Accuracy vs. performance in parallel simulation of interconnection networks. In Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 22-31, IEEE Computer Society, 1995.
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• Mark D. Hill, James R. Larus, and David A. Wood. Tempest: A Substrate for Portable Parallel Programs. In COMPCON '95: Technologies for the Information Superhighway, Digest of Papers, San Francisco, California, USA, March 5-9, 1995, pp. 327-332, IEEE Computer Society, 1995.
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• Alvin R. Lebeck and David A. Wood. Dynamic Self-Invalidation: Reducing Coherence Overhead in Shared-Memory Multiprocessors. In Proceedings of the 22nd Annual International Symposium on Computer Architecture, ISCA '95, Santa Margherita Ligure, Italy, June 22-24, 1995, pp. 48-59, ACM, 1995.
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• Alvin R. Lebeck and David A. Wood. Active Memory: A New Abstraction for Memory-System Simulation. In Proceedings of the 1995 ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems, Ottawa, Canada, May 15-19, 1995, pp. 220-231, ACM, 1995.
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• Ted G. Lewis, Dave Power, Bertrand Meyer, Jack Grimes, Mike Potel, Ronald J. Vetter, Phillip A. Laplante, Wolfgang Pree, Gustav Pomberger, Mark D. Hill, James R. Larus, David A. Wood, Hesham El-Rewini, and Bruce W. Weide. Where Is Software Headed? A Virtual Roundtable. Computer, 28(8):20-32, 1995.
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• David A. Wood and Mark D. Hill. Cost-Effective Parallel Computing. Computer, 28(2):69-72, 1995.
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• Doug Burger, Rahmat S. Hyder, Barton P. Miller, and David A. Wood. Paging tradeoffs in distributed-shared-memory multiprocessors. In Proceedings Supercomputing '94, Washington, DC, USA, November 14-18, 1994, pp. 590-599, IEEE Computer Society, 1994.
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• Babak Falsafi, Alvin R. Lebeck, Steven K. Reinhardt, Ioannis Schoinas, Mark D. Hill, James R. Larus, Anne Rogers, and David A. Wood. Application-specific protocols for user-level shared memory. In Proceedings Supercomputing '94, Washington, DC, USA, November 14-18, 1994, pp. 380-389, IEEE Computer Society, 1994.
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• Mark D. Hill, James R. Larus, and David A. Wood. The Wisconsin Wind Tunnel project: an annotated bibliography. SIGARCH Comput. Archit. News, 22(5):19-26, 1994.
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• Richard E. Kessler, Mark D. Hill, and David A. Wood. A Comparison of Trace-Sampling Techniques for Multi-Megabyte Caches. IEEE Trans. Computers, 43(6):664-675, 1994.
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• Alvin R. Lebeck and David A. Wood. Cache Profiling and the SPEC Benchmarks: A Case Study. Computer, 27(10):15-26, 1994.
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• Steven K. Reinhardt, James R. Larus, and David A. Wood. Tempest and Typhoon: User-Level Shared Memory. In Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, IL, USA, April 1994, pp. 325-336, IEEE Computer Society, 1994.
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• Ioannis Schoinas, Babak Falsafi, Alvin R. Lebeck, Steven K. Reinhardt, James R. Larus, and David A. Wood. Fine-grain Access Control for Distributed Shared Memory. In ASPLOS-VI Proceedings - Sixth International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, USA, October 4-7, 1994, pp. 297-306, ACM Press, 1994.
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• Mark D. Hill, James R. Larus, Alvin R. Lebeck, Madhusudhan Talluri, and David A. Wood. Wisconsin Architectural Research Tool Set. SIGARCH Comput. Archit. News, 21(4):8-10, 1993.
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• Mark D. Hill, James R. Larus, Steven K. Reinhardt, and David A. Wood. Cooperative Shared Memory: Software and Hardware Support for Scalable Multiprocesors. ACM Trans. Comput. Syst., 11(4):300-318, 1993.
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• Steven K. Reinhardt, Babak Falsafi, and David A. Wood. Kernel Support for the Wisconsin Wind Tunnel. In USENIX Microkernels and Other Kernel Architectures Symposium, September 20-23, 1993, San Diego, California, USA, pp. 73-90, USENIX, 1993.
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• Steven K. Reinhardt, Mark D. Hill, James R. Larus, Alvin R. Lebeck, James C. Lewis, and David A. Wood. The Wisconsin Wind Tunnel: Virtual Prototyping of Parallel Computers. In Proceedings of the 1993 ACM SIGMETRICS conference on Measurement and modeling of computer systems, Santa Clara, California, USA, May 10-14, 1993, pp. 48-60, ACM, 1993.
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• David A. Wood, Satish Chandra, Babak Falsafi, Mark D. Hill, James R. Larus, Alvin R. Lebeck, James C. Lewis, Shubhendu S. Mukherjee, Subbarao Palacharla, and Steven K. Reinhardt. Mechanisms for Cooperative Shared Memory. In Proceedings of the 20th Annual International Symposium on Computer Architecture, San Diego, CA, USA, May 1993, pp. 156-167, ACM, 1993.
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• Mark D. Hill, James R. Larus, Steven K. Reinhardt, and David A. Wood. Cooperative Shared Memory: Software and Hardware Support for Scalable Multiprocesors. In ASPLOS-V Proceedings - Fifth International Conference on Architectural Support for Programming Languages and Operating Systems, Boston, Massachusetts, USA, October 12-15, 1992, pp. 262-273, ACM Press, 1992.
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• Yul H. Kim, Mark D. Hill, and David A. Wood. Implementing Stack Simulation for Highly-Associative Memories. In Proceedings of the 1991 ACM SIGMETRICS conference on Measurement and modeling of computer systems, San Diego, California, USA, May 21-24, 1991, pp. 212-213, ACM, 1991.
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• David A. Wood, Mark D. Hill, and Richard E. Kessler. A Model for Estimating Trace-Sample Miss Ratios. In Proceedings of the 1991 ACM SIGMETRICS conference on Measurement and modeling of computer systems, San Diego, California, USA, May 21-24, 1991, pp. 79-89, ACM, 1991.
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• David A. Wood, Garth A. Gibson, and Randy H. Katz. Verifying a Multiprocessor Cache Controller Using Random Test Generation. IEEE Des. Test Comput., 7(4):13-25, 1990.
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• David A. Wood and Randy H. Katz. Supporting Reference and Dirty Bits in SPUR's Virtual Address Cache. In Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, Israel, June 1989, pp. 122-130, ACM, 1989.
  Details   
• David A. Wood, Susan J. Eggers, Garth A. Gibson, Mark D. Hill, Joan M. Pendleton, Scott A. Ritchie, George S. Taylor, Randy H. Katz, and David A. Patterson. An In-Cache Address Translation Mechanism. In Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, pp. 358-365, IEEE Computer Society, 1986.
  Details   
• Randy H. Katz, Susan J. Eggers, David A. Wood, Charles L. Perkins, and Robert G. Sheldon. Implementing A Cache Consistency Protocol. In Proceedings of the 12th Annual Symposium on Computer Architecture, Boston, MA, USA, June 1985, pp. 276-283, IEEE Computer Society, 1985.
  Details   
• David J. DeWitt, Randy H. Katz, Frank Olken, Leonard D. Shapiro, Michael Stonebraker, and David A. Wood. Implementation Techniques for Main Memory Database Systems. In SIGMOD'84, Proceedings of Annual Meeting, Boston, Massachusetts, USA, June 18-21, 1984, pp. 1-8, ACM Press, 1984.
  Details   

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