» Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors

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Gurindar S. Sohi. Cache Memory Organization to Enhance the Yield of High-Performance VLSI Processors. IEEE Trans. Computers, 38(4):484-492, 1989.

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BibTeX

 @article{DBLP:journals/tc/Sohi89,
   author    = {Gurindar S. Sohi},
   title     = {Cache Memory Organization to Enhance the Yield of High-Performance
                {VLSI} Processors},
   journal   = {{IEEE} Trans. Computers},
   volume    = {38},
   number    = {4},
   pages     = {484--492},
   year      = {1989},
   url       = {https://doi.org/10.1109/12.21141},
   doi       = {10.1109/12.21141},
   timestamp = {Sat, 20 May 2017 01:00:00 +0200},
   biburl    = {https://dblp.org/rec/journals/tc/Sohi89.bib},
   bibsource = {dblp computer science bibliography, https://dblp.org}
 }

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