| Name | Advisor | Year | PhD Dissertation Title |
| David Schlais | Mikko Lipasti | December 2020 | Modeling and Designing Secure Tightly-Coupled Accelerators in CPUs |
| Gokul Ravi | Mikko Lipasti | August 2020 | Integrating Computing Systems from the Gates up: Breaking the Clock Abstraction |
| Swapnil Haria | Mark Hill | Aug 2019 | Architecture and Software Support for Persistent and Vast Memory |
| | Michael M. Swift | | |
| Michael Mishkin | Mikko Lipasti | June 2019 | Efficient Inference Acceleration |
| Rohit Shukla | Mikko Lipasti | Aug 2018 | Addressing the Algorithmic Gap in Low-Precision Neural Network Substrates |
| Vinay Gangadhar | Karu Sankaralingam | Fall 2017 | Programmable Hardware Acceleration |
| Dibakar Gope | Mikko Lipasti | June 2017 | Architectural Support for Scripting Languages |
| Vijayaraghavan Thiruvengada | Karu Sankaralingam | Summer 2017 | Memory Processing Units |
| Jason Lowe-Power | Mark Hill | June 2017 | On Hetergeneous Compute and Memory Systems |
| | David A. Wood. | | |
| Nilay Vaish | David A. Wood | May 2017 | Optimization-based Models for Pruning the Design-space for Processors |
| Hongil Yoon | Guri Sohi | March 2017 | Reducing Address Translation Overheads with Virtual Caching |
| Muhammad Shoaib Bin Altaf | David A. Wood | December 2016 | Exploiting Simple Analytical Models for Modeling Hardware Accelerators |
| Tony Nowatzki | Karu Sankaralingam | Fall 2016 | Behavior Specialized Processors |
| Marc Orr | David A. Wood | December 2016 | Communication and Coordination Paradigms for Highly-parallel Accelerators |
| Joel Hestness | David A. Wood | November 2016 | Synchronization and Coordination in Heterogeneous Processors |
| | Stephen W. Keckler | | |
| Newsha Ardalani | Karu Sankaralingam | Fall 2016 | Cross-Architecture Performance Prediction and Analysis Using Machine Learning |
| Jayneel Gandhi | Mark D. Hill | Aug 2016 | Efficient Memory Virtualization |
| | Michael M. Swift | | |
| Lena E. Olson | Mark D. Hill | Aug 2016 | Protecting Host Systems from Imperfect Hardware Accelerators |
| Rathijit Sen | David A. Wood. | Aug 2016 | Energy-Efficient Management of Reconfigurable Computers |
| Gagan Gupta | Guri Sohi | June 2015 | Semantically Ordered Parallel Execution of Multiprocessor Programs |
| David Palframan | Mikko Lipasti | May 2015 | Cost-effective techniques for processor reliability |
| Somayeh Sardashti | David A. Wood | May 2015 | Using Compression for Energy-Optimized Memory Hierarchies |
| Sung Jin Kim | Karu Sankaralingam | Spring 2015 | High-Level Synthesis for Efficient Accelerator Design |
| Srinath Sridharan | Guri Sohi | October 2014 | Adaptive, Efficient Parallel Execution of Parallel Programs |
| Chen-Han Ho | Karu Sankaralingam | Fall 2014 | Mechanisms Towards Energy-Efficient Dynamic Hardware Specialization |
| Vignyan Reddy Kothinti Naresh | Mikko Lipasti | August 2014 | Express Misprediction Recovery |
| Sean Franey | Mikko Lipasti | August 2014 | Tag Tables |
| Arslan Zulfiqar | Mikko Lipasti | August 2014 | Efficient Architectures for Multichip Communication |
| Venkatraman Govindaraju | Karu Sankaralingam | Summer 2014 | Energy Efficient Computing through Compiler Assisted Dynamic Specialization |
| Arkaprava (Arka) Basu | Mark D. Hill | Dec 2013 | Revisiting Virtual Memory |
| | Michael M. Swift | | |
| Emily Blem | Karu Sankaralingam | Summer 2013 | Unified Models to Study Multicore Scaling Limits and Accelerator-Based Solutions |
| Mitch Hayenga | Mikko Lipasti | Aug 2013 | Power-efficient Loop Execution Techniques |
| Andrew Nere | Mikko Lipasti | May 2013 | Complex Neural Computation with Simple Digital Neurons |
| Marc de Kruijf | Karu Sankaralingam | Jul-12 | Compiler Construction of Idempotent Regions and Applications in Architecture Design |
| Derek R. Hower | Mark D. Hill | July 2012 | Acoherent Shared Memory |
| Atif Hashmi | Mikko Lipasti | December 2011 | Cortical Columns: A Non-von Neumann Computational Abstraction |
| Yasuko Watanabe | David A. Wood | December 2011 | On Power-Proportional Processors |
| Dan Gibson | David Wood | Dec-10 | Scalable Cores in Chip Multiprocessors |
| Dana Vantrease | Mikko Lipasti | Aug-10 | Optical Tokens in Many-Core processors |
| Matthew Allen | Guri Sohi | Aug-10 | Data-Driven Decomposition of Sequential Programs for Determinate Parallel Execution |
| Erika Gunadi | Mikko Lipasti | May-10 | "CRIB: Consolidated Rename, Issue, and Bypass" |
| Jayaram Bobba | Mark D. Hill | Feb-10 | Hardware Support for Efficient Transactional and Supervised Memory Systems |
| Kyle Nesbit | Jim Smith | May-09 | Virtual Private Machines: A Resource Abstraction for Multicore Computer Systems |
| Luke Yen | Mark D. Hill | Feb-09 | Signatures in Transactional Memory Systems |
| Natalie Enright Jerger | Mikko Lipasti | Dec-08 | Chip Multiprocessor Coherence and Interconnect System Design |
| | Li-Shiuan Peh (Princeton) | | |
| Eric L Hill | Mikko Lipasti | Dec-08 | Understanding and Mitigating the Effects of Soft Errors in Logic |
| Koushik Chakraborty | Guri Sohi | Aug-08 | Over-provisioned Multicore Systems |
| Lixin Su | Mikko Lipasti | Aug-08 | Streamlined Atomic Execution for Java |
| Philip Wells | Guri Sohi | Jul-08 | Adapting to Dynamic Heterogeneity: Virtualization for the Multicore Era |
| Michael R. Marty | Mark D. Hill | Jan-08 | Cache Coherence Techniques for Multicore Processors |
| Nidhi Aggarwal | Jim Smith | May-08 | Achieving High Availability with Commodity Hardware and Software |
| Gordon Bell | Mikko Lipasti | Dec-07 | Latency- and Error-Tolerant Redundant Execution |
| Jichuan Chang | Guri Sohi | Aug-07 | Cooperative Caching for Chip Multiprocessors |
| Kevin Moore | David Wood | Jun-07 | Log-based Transactional Memory |
| Saisanthosh Balakrishnan | Guri Sohi | Jan-07 | Program Demultiplexing: Data-flow Based Speculative Parallelization of Methods in Sequential Programs |
| Tejas Karkhanis | Jim Smith | May-06 | Automated Design of Application-Specific Superscalar Processors |
| Min Xu | Mark Hill | May-06 | Race Recording for Multithreaded Deterministic Replay Using Multiprocessor Hardware |
| | Ras Bodik | | |
| Brad Beckmann | David Wood | May-06 | Managing Wire Delay in Chip Multiprocessor Caches |
| Jason Cantin | Mikko Lipasti | May-06 | Coarse-grain Coherence Tracking |
| | James E Smith | | |
| Shiliang Hu | Jim Smith | Mar-06 | Efficient Binary Translation in Co-Designed Virtual Machines |
| Alaa Alameldeen | David Wood | Mar-06 | Using Compression to Improve Chip Multiprocessor Performance |
| Ho-Seop Kim | Jim Smith | Dec-04 | A Co-designed Virtual Machine for Instruction-Level Distributed Processing (ILDP) |
| Ashutosh Dhodapkar | Jim Smith | Dec-04 | Automatic Management of Adaptive Microarchitctures |
| Trey Cain | Mikko Lipasti | Dec-04 | Detecting and Exploiting Causal Relationships in Hardware Shared-Memory Multiprocessors |
| J. Adam Butts | Guri Sohi | Aug-04 | Optimizing Inter-Instruction Value Communication through Degree of Use Prediction |
| Ilhyun Kim | Mikko Lipasti | May-04 | Macro-op Scheduling and Execution |
| Milo Martin | Mark Hill | Dec-03 | Token Coherence |
| Kevin Lepak | Mikko Lipasti | Sep-03 | "Exploring, Defining, and Exploiting Recent Store Value Locality" |
| S. Subramanya Sastry | Jim Smith | Jan-03 | Techniques for Transparent Runtime Program Specialization Within Dynamic Optimzation Systems |
| | Rastislav Bodik | | |
| Ravi Rajwar | Jim Goodman | Sep-02 | Speculation-Based Techniques for Transactional Lock-Free Execution of Lock-Based Programs |
| Craig Zilles | Guri Sohi | Aug-02 | Master/Slave Speculative Parallelization and Approximate Code |
| Daniel Sorin | David Wood | Aug-02 | Using Lightweight Checkpoint/Recovery to Improve the Availability and Designability of Shared Memory Multiprocessors |
| Timothy Heil | Jim Smith | Aug-02 | Relational Profiling in Multithreaded Virtual Machines |
| Amir Roth | Guri Sohi | Aug-01 | Pre-Execution via Speculative Data-Driven Multithreading |
| Avinash Sodani | Guri Sohi | Mar-00 | Dynamic Instruction Reuse |
| Eric Rotenberg | Jim Smith | Sep-99 | Trace Processors: Exploiting Hierarchy and Speculation |
| Trishul Chilimbi | James Larus | Aug-99 | Cache-Conscious Data Structures--Design and Implementation |
| | Mark Hill | | |
| Quinn Jacobson | Jim Smith | Aug-99 | High-Performance Front-ends for Trace Processors |
| Yanos Sazeides | Jim Smith | Aug-99 | An Analysis of Value Predictability and its Application to a Superscalar Processor |
| Alain Kägi | Jim Goodman | Jan-99 | "Mechanisms for Efficient Shared-memory, Lock-based Synchronization" |
| Andreas Moshovos | Guri Sohi | Dec-98 | Memory Dependence Prediction |
| Doug Burger | Jim Goodman | Dec-98 | Hardware Techniques to Improve the Performance of the Processor/Memory Interface |
| Scott Breach | Guri Sohi | Dec-98 | Design and Evaluation of a Multiscalar Processor |
| Stefanos Kaxiras | Jim Goodman | Aug-98 | Identification and Optimization of Sharing Patterns for Scalable Shared-Memory Multiprocessors |
| Shubu Mukherjee | Mark Hill | May-98 | Design and Evaluation of Network Interfaces for System Area Networks |
| Subbarao Palacharla | Jim Smith | Feb-98 | Complexity-Effective Superscalar Processors |
| T.N. Vijaykumar | Guri Sohi | Jan-98 | Compiling for the Multiscalar Architecture |
| Babak Falsafi | David Wood | Dec-97 | Fine-Grain Protocol Execution Mechanisms & Scheduling Policies on SMP Clusters |
| Ioannis Schoinas | Mark Hill | Dec-97 | Fine-Grain Distributed Shared Memory Systems on Clusters of Workstations |
| Steven K. Reinhardt | David Wood | Dec-96 | Mechanisms for Distributed Shared Memory |
| Todd M. Austin | Guri Sohi | Apr-96 | Hardware and Software Mechanisms for Reducing Load Latency |
| Dionisios Pnevmatikatos | Guri Sohi | Dec-95 | Incorporating Guarded Execution in Existing Instruction Sets |
| Alvin R. Lebeck | David Wood | Nov-95 | Tools and Techniques for Memory System Design and Analysis |
| Madhusudhan Talluri | Mark Hill | Aug-95 | Use of Superpages and Subblocking in the Address Translation Hierarchy |
| Manoj Franklin | Guri Sohi | Dec-93 | The Multiscalar Architecture |
| Sarita V. Adve | Mark Hill | Nov-93 | Designing Memory Consistency Models for Shared-Memory Multiprocessors |
| Ross Johnson | Jim Goodman | Jun-93 | Extending the Scalable Coherent Interface for Large-Scale Shared-Memory |
| Steve Scott | Jim Goodman | Aug-92 | "Toward the Design of Large-Scale, Shared-Memory Multiprocessors" |
| Mark Friedman | Guri Sohi | Jan-92 | An Architectural Characterization of Prolog Execution |
| Sriram Vajapeyam | Guri Sohi | Dec-91 | Instruction Level Characterization of the Cray Y-MP Processor |
| Men-Chow Chiang | Guri Sohi | Sep-91 | Memory System Design for Bus Based Multiprocessors |
| Richard E. Kessler | Mark Hill | Jul-91 | Analysis of Multi-Megabyte Secondary CPU Cache Memories |
| Matthew K. Farrens | Andy Pleszkun | Aug-89 | The Design and Analysis of a High Performance Single Chip Processor |
| Wei-Chung Hsu | Jim Goodman | Aug-87 | Register Allocation and Code Scheduling for Load/Store Architectures |
| Steve Kunkel | Jim Smith | 1987 | Pipelined Processing of Fine-grain Parallelism |
| William Cox | Bob Cook | Aug-86 | The Performance of Disk Servers |
| | Jim Goodman | | |
| Koujuch Liou | Jim Goodman | Aug-85 | Design of Pipelined Memory Systems for Decoupled Architectures |
| Honesty C. Young | Jim Goodman | Jun-85 | Evaluation of a Decoupled Computer Architecture and the Design of a Vector Extension |
| Michael Scott | Raphael Finkel | May-85 | Design and Implementation of a Distributed Systems Language |
| Shlomo Weiss | Jim Smith | Jan-84 | Very High Performance Scalar Processing |
| Craig Holt | Jim Smith | 1981 | Diagnosis and Self Diagnosis of Digital Systems |