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Alumni with PHDs from the Wisconsin Computer Architecture Group

NameAdvisorYearPhD Dissertation Title
David SchlaisMikko LipastiDecember 2020Modeling and Designing Secure Tightly-Coupled Accelerators in CPUs
Gokul RaviMikko LipastiAugust 2020Integrating Computing Systems from the Gates up: Breaking the Clock Abstraction
Swapnil HariaMark HillAug 2019Architecture and Software Support for Persistent and Vast Memory
 Michael M. Swift  
Michael MishkinMikko LipastiJune 2019Efficient Inference Acceleration
Rohit ShuklaMikko LipastiAug 2018Addressing the Algorithmic Gap in Low-Precision Neural Network Substrates
Vinay GangadharKaru SankaralingamFall 2017Programmable Hardware Acceleration
Dibakar GopeMikko LipastiJune 2017Architectural Support for Scripting Languages
Vijayaraghavan ThiruvengadaKaru SankaralingamSummer 2017Memory Processing Units
Jason Lowe-PowerMark HillJune 2017On Hetergeneous Compute and Memory Systems
 David A. Wood.  
Nilay VaishDavid A. WoodMay 2017Optimization-based Models for Pruning the Design-space for Processors
Hongil YoonGuri SohiMarch 2017Reducing Address Translation Overheads with Virtual Caching
Muhammad Shoaib Bin AltafDavid A. WoodDecember 2016Exploiting Simple Analytical Models for Modeling Hardware Accelerators
Tony NowatzkiKaru SankaralingamFall 2016Behavior Specialized Processors
Marc OrrDavid A. WoodDecember 2016Communication and Coordination Paradigms for Highly-parallel Accelerators
Joel HestnessDavid A. WoodNovember 2016Synchronization and Coordination in Heterogeneous Processors
 Stephen W. Keckler  
Newsha ArdalaniKaru SankaralingamFall 2016Cross-Architecture Performance Prediction and Analysis Using Machine Learning
Jayneel GandhiMark D. HillAug 2016Efficient Memory Virtualization
 Michael M. Swift  
Lena E. OlsonMark D. HillAug 2016Protecting Host Systems from Imperfect Hardware Accelerators
Rathijit SenDavid A. Wood.Aug 2016Energy-Efficient Management of Reconfigurable Computers
Gagan GuptaGuri SohiJune 2015Semantically Ordered Parallel Execution of Multiprocessor Programs
David PalframanMikko LipastiMay 2015Cost-effective techniques for processor reliability
Somayeh SardashtiDavid A. WoodMay 2015Using Compression for Energy-Optimized Memory Hierarchies
Sung Jin KimKaru SankaralingamSpring 2015High-Level Synthesis for Efficient Accelerator Design
Srinath SridharanGuri SohiOctober 2014Adaptive, Efficient Parallel Execution of Parallel Programs
Chen-Han HoKaru SankaralingamFall 2014Mechanisms Towards Energy-Efficient Dynamic Hardware Specialization
Vignyan Reddy Kothinti NareshMikko LipastiAugust 2014Express Misprediction Recovery
Sean FraneyMikko LipastiAugust 2014Tag Tables
Arslan ZulfiqarMikko LipastiAugust 2014Efficient Architectures for Multichip Communication
Venkatraman GovindarajuKaru SankaralingamSummer 2014Energy Efficient Computing through Compiler Assisted Dynamic Specialization
Arkaprava (Arka) BasuMark D. HillDec 2013Revisiting Virtual Memory
 Michael M. Swift  
Emily BlemKaru SankaralingamSummer 2013Unified Models to Study Multicore Scaling Limits and Accelerator-Based Solutions
Mitch HayengaMikko LipastiAug 2013Power-efficient Loop Execution Techniques
Andrew NereMikko LipastiMay 2013Complex Neural Computation with Simple Digital Neurons
Marc de KruijfKaru SankaralingamJul-12Compiler Construction of Idempotent Regions and Applications in Architecture Design
Derek R. HowerMark D. HillJuly 2012Acoherent Shared Memory
Atif HashmiMikko LipastiDecember 2011Cortical Columns: A Non-von Neumann Computational Abstraction
Yasuko WatanabeDavid A. WoodDecember 2011On Power-Proportional Processors
Dan GibsonDavid WoodDec-10Scalable Cores in Chip Multiprocessors
Dana VantreaseMikko LipastiAug-10Optical Tokens in Many-Core processors
Matthew AllenGuri SohiAug-10Data-Driven Decomposition of Sequential Programs for Determinate Parallel Execution
Erika GunadiMikko LipastiMay-10"CRIB: Consolidated Rename, Issue, and Bypass"
Jayaram BobbaMark D. HillFeb-10Hardware Support for Efficient Transactional and Supervised Memory Systems
Kyle NesbitJim SmithMay-09Virtual Private Machines: A Resource Abstraction for Multicore Computer Systems
Luke YenMark D. HillFeb-09Signatures in Transactional Memory Systems
Natalie Enright JergerMikko LipastiDec-08Chip Multiprocessor Coherence and Interconnect System Design
 Li-Shiuan Peh (Princeton)  
Eric L HillMikko LipastiDec-08Understanding and Mitigating the Effects of Soft Errors in Logic
Koushik ChakrabortyGuri SohiAug-08Over-provisioned Multicore Systems
Lixin SuMikko LipastiAug-08Streamlined Atomic Execution for Java
Philip WellsGuri SohiJul-08Adapting to Dynamic Heterogeneity: Virtualization for the Multicore Era
Michael R. MartyMark D. HillJan-08Cache Coherence Techniques for Multicore Processors
Nidhi AggarwalJim SmithMay-08Achieving High Availability with Commodity Hardware and Software
Gordon BellMikko LipastiDec-07Latency- and Error-Tolerant Redundant Execution
Jichuan ChangGuri SohiAug-07Cooperative Caching for Chip Multiprocessors
Kevin MooreDavid WoodJun-07Log-based Transactional Memory
Saisanthosh BalakrishnanGuri SohiJan-07Program Demultiplexing: Data-flow Based Speculative Parallelization of Methods in Sequential Programs
Tejas KarkhanisJim SmithMay-06Automated Design of Application-Specific Superscalar Processors
Min XuMark HillMay-06Race Recording for Multithreaded Deterministic Replay Using Multiprocessor Hardware
 Ras Bodik  
Brad BeckmannDavid WoodMay-06Managing Wire Delay in Chip Multiprocessor Caches
Jason CantinMikko LipastiMay-06Coarse-grain Coherence Tracking
 James E Smith  
Shiliang HuJim SmithMar-06Efficient Binary Translation in Co-Designed Virtual Machines
Alaa AlameldeenDavid WoodMar-06Using Compression to Improve Chip Multiprocessor Performance
Ho-Seop KimJim SmithDec-04A Co-designed Virtual Machine for Instruction-Level Distributed Processing (ILDP)
Ashutosh DhodapkarJim SmithDec-04Automatic Management of Adaptive Microarchitctures
Trey CainMikko LipastiDec-04Detecting and Exploiting Causal Relationships in Hardware Shared-Memory Multiprocessors
J. Adam ButtsGuri SohiAug-04Optimizing Inter-Instruction Value Communication through Degree of Use Prediction
Ilhyun KimMikko LipastiMay-04Macro-op Scheduling and Execution
Milo MartinMark HillDec-03Token Coherence
Kevin LepakMikko LipastiSep-03"Exploring, Defining, and Exploiting Recent Store Value Locality"
S. Subramanya SastryJim SmithJan-03Techniques for Transparent Runtime Program Specialization Within Dynamic Optimzation Systems
 Rastislav Bodik  
Ravi RajwarJim GoodmanSep-02Speculation-Based Techniques for Transactional Lock-Free Execution of Lock-Based Programs
Craig ZillesGuri SohiAug-02Master/Slave Speculative Parallelization and Approximate Code
Daniel SorinDavid WoodAug-02Using Lightweight Checkpoint/Recovery to Improve the Availability and Designability of Shared Memory Multiprocessors
Timothy HeilJim SmithAug-02Relational Profiling in Multithreaded Virtual Machines
Amir RothGuri SohiAug-01Pre-Execution via Speculative Data-Driven Multithreading
Avinash SodaniGuri SohiMar-00Dynamic Instruction Reuse
Eric RotenbergJim SmithSep-99Trace Processors: Exploiting Hierarchy and Speculation
Trishul ChilimbiJames LarusAug-99Cache-Conscious Data Structures--Design and Implementation
 Mark Hill  
Quinn JacobsonJim SmithAug-99High-Performance Front-ends for Trace Processors
Yanos SazeidesJim SmithAug-99An Analysis of Value Predictability and its Application to a Superscalar Processor
Alain KägiJim GoodmanJan-99"Mechanisms for Efficient Shared-memory, Lock-based Synchronization"
Andreas MoshovosGuri SohiDec-98Memory Dependence Prediction
Doug BurgerJim GoodmanDec-98Hardware Techniques to Improve the Performance of the Processor/Memory Interface
Scott BreachGuri SohiDec-98Design and Evaluation of a Multiscalar Processor
Stefanos KaxirasJim GoodmanAug-98Identification and Optimization of Sharing Patterns for Scalable Shared-Memory Multiprocessors
Shubu MukherjeeMark HillMay-98Design and Evaluation of Network Interfaces for System Area Networks
Subbarao PalacharlaJim SmithFeb-98Complexity-Effective Superscalar Processors
T.N. VijaykumarGuri SohiJan-98Compiling for the Multiscalar Architecture
Babak FalsafiDavid WoodDec-97Fine-Grain Protocol Execution Mechanisms & Scheduling Policies on SMP Clusters
Ioannis SchoinasMark HillDec-97Fine-Grain Distributed Shared Memory Systems on Clusters of Workstations
Steven K. ReinhardtDavid WoodDec-96Mechanisms for Distributed Shared Memory
Todd M. AustinGuri SohiApr-96Hardware and Software Mechanisms for Reducing Load Latency
Dionisios PnevmatikatosGuri SohiDec-95Incorporating Guarded Execution in Existing Instruction Sets
Alvin R. LebeckDavid WoodNov-95Tools and Techniques for Memory System Design and Analysis
Madhusudhan TalluriMark HillAug-95Use of Superpages and Subblocking in the Address Translation Hierarchy
Manoj FranklinGuri SohiDec-93The Multiscalar Architecture
Sarita V. AdveMark HillNov-93Designing Memory Consistency Models for Shared-Memory Multiprocessors
Ross JohnsonJim GoodmanJun-93Extending the Scalable Coherent Interface for Large-Scale Shared-Memory
Steve ScottJim GoodmanAug-92"Toward the Design of Large-Scale, Shared-Memory Multiprocessors"
Mark FriedmanGuri SohiJan-92An Architectural Characterization of Prolog Execution
Sriram VajapeyamGuri SohiDec-91Instruction Level Characterization of the Cray Y-MP Processor
Men-Chow ChiangGuri SohiSep-91Memory System Design for Bus Based Multiprocessors
Richard E. KesslerMark HillJul-91Analysis of Multi-Megabyte Secondary CPU Cache Memories
Matthew K. FarrensAndy PleszkunAug-89The Design and Analysis of a High Performance Single Chip Processor
Wei-Chung HsuJim GoodmanAug-87Register Allocation and Code Scheduling for Load/Store Architectures
Steve KunkelJim Smith1987Pipelined Processing of Fine-grain Parallelism
William CoxBob CookAug-86The Performance of Disk Servers
 Jim Goodman  
Koujuch LiouJim GoodmanAug-85Design of Pipelined Memory Systems for Decoupled Architectures
Honesty C. YoungJim GoodmanJun-85Evaluation of a Decoupled Computer Architecture and the Design of a Vector Extension
Michael ScottRaphael FinkelMay-85Design and Implementation of a Distributed Systems Language
Shlomo WeissJim SmithJan-84Very High Performance Scalar Processing
Craig HoltJim Smith1981Diagnosis and Self Diagnosis of Digital Systems

Page last modified on November 05, 2021