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Publications by Multiscalar People

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[2008] [2007] [2006] [2005] [2004] [2003] [2002] [2001] [2000] [1999] [1998] [1997] [1996] [1995] [1994] [1993] [1992] [Theses]

2008

• Adapting to Intermittent Faults in Multicore Systems
  Philip M. Wells, Koushik Chakraborty, and Gurindar S. Sohi.
  13th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XIII), March 2008
  Abstract
• Serializing Instruction in System-Intensive Workloads: Amdahl's Law Strikes Again
  Philip M. Wells and Gurindar S. Sohi.
  14th International Symposium on High-Performance Computer Architecture (HPCA-08), Feb. 2008
  Abstract

2007

• Cooperative Cache Partitioning for Chip Multiprocessors
  Jichaun Chang and Gurindar S. Sohi
  21st International Conference on Supercomputing (ICS'07), June, 2007
  Abstract

2006

• Computation Spreading: Employing Hardware Migration to Specialize CMP Cores On-the-fly
  Koushik Chakraborty, Philip M. Wells, and Gurindar S. Sohi
  12th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XII), Nov. 2006
  Abstract
• Hardware Support for Spin Management in Overcommitted Virtual Machines
  Philip M. Wells, Koushik Chakraborty, and Gurindar S. Sohi
  15th International Conference on Parallel Architectures and Compilation Techniques (PACT-2006), Sept. 2006
  Abstract
• Program Demultiplexing: Data-flow based Speculative Execution of Methods in Sequential Programs
  Saisanthosh Balakrishnan and Gurindar S. Sohi
  33th annual International Symposium on Computer Architecture (ISCA-33), June 2006
  Abstract
• Cooperative Caching for Chip Multiprocessors
  Jichaun Chang and Gurindar S. Sohi
  33th annual International Symposium on Computer Architecture (ISCA-33), June 2006
  Abstract

2005

• The Impact of Performance Asymmetry in Emerging Multicore Architectures
  Saisanthosh Balakrishnan, Ravi Rajwar, Mike Upton and Konrad Lai
  32th annual International Symposium on Computer Architecture (ISCA-32), June 2005
  Abstract

2004

• Characterization of Problem Stores
  Allison L. Holloway and Gurindar S. Sohi
  Computer Architecture Letters, Volume 3, Dec. 2004
  Abstract

• Coherence Decoupling: Making Use of Incoherence
  Jaehyuk Huh, Jichuan Chang, Doug Burger, and Gurindar S. Sohi
  11th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), Oct 2004
  Abstract

• Use Based Register Caching with Decoupled Indexing
  J. Adam Butts and Gurindar S. Sohi
  The 31th International Symposium on Computer Architecture (ISCA-31), 2004.
  Abstract

2003

• Exploiting Value Locality in Physical Register Files
  Saisanthosh Balakrishnan and Gurindar S. Sohi
  36th International Symposium on Microarchitecture (MICRO-36), Dec. 3-5, 2003.
  Abstract

• Parallelism in the Front-End
  Paramjit S. Oberoi and Gurindar S. Sohi
  The 30th International Symposium on Computer Architecture (ISCA-30), June 9-11, 2003.
  Abstract

• Using Coherence Value Speculation to Improve Multiprocessor Performance
  Jichaun Chang, Jaehyuk Huh, Rajagopalan Desikan, Doug Burger, Gurindar Sohi
  First Value-Prediction Workshop (at ISCA-30), June 7, 2003.
  Abstract

2002

• Characterizing and Predicting Value Degree of Use
  J. Adam Butts and Gurindar S. Sohi
  35th International Symposium on Microarchitecture (MICRO-35), Nov. 18-22, 2002.
  Abstract

• A Quantitative Framework for Automated Pre-Execution Thread Selection
  Amir Roth and G.S. Sohi
  35th International Symposium on Microarchitecture (MICRO-35), Nov. 18-22, 2002.
  

• Master/Slave Speculative Parallelization
  Craig Zilles and G.S. Sohi
  35th International Symposium on Microarchitecture (MICRO-35), Nov. 18-22, 2002.
  

• Dynamic Dead-Instruction Detection and Elimination
  J. Adam Butts and Gurindar S. Sohi
  10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), Oct 2002
  Abstract

• Out-of-Order Instruction Fetch using Multiple Sequencers
  Paramjit S. Oberoi and Gurindar S. Sohi
  The 2002 International Conference on Parallel Processing (ICPP-31), Aug. 18-21, 2002
  Abstract

2001

• Execution-based Prediction Using Speculative Slices
  Craig B. Zilles and Gurindar S. Sohi
  28th International Symposium on Computer Architecture (ISCA-28), July 2001.
  Abstract

• A Programmable Co-processor for Profiling
  Craig B. Zilles and Gurindar S. Sohi
  7th International Symposium on High Performance Computer Architecture (HPCA-7), Jan. 20-24 2001.
  Abstract

• Speculative Data-Driven Multithreading
  Amir Roth and Gurindar S. Sohi
  7th International Symposium on High Performance Computer Architecture (HPCA-7), Jan. 20-24 2001.
  Abstract

2000

• Speculative Multithreaded Processors
  Gurindar S. Sohi and Amir Roth
  International Conference on High Performance Computing (HiPC-00), Dec. 17-20, 2000.
  

• A Static Power Model for Architects
  J. Adam Butts and Gurindar S. Sohi
  33rd International Symposium on Microarchitecture (MICRO-33), Dec. 10-13, 2000.
  Abstract

• Register Integration: A Simple and Efficient Implementation of Squash Reuse
  Amir Roth and Gurindar S. Sohi
  33rd International Symposium on Microarchitecture (MICRO-33), Dec. 10-13, 2000.
  Abstract

• Speculative Miss/Execute Decoupling
  Amir Roth, Craig B. Zilles and Gurindar S. Sohi
  MEDEA Workshop, Oct. 19, 2000.
  Abstract

• Understanding the Backward Slices of Performance Degrading Instructions
  Craig B. Zilles and Gurindar S. Sohi
  27th International Symposium on Computer Architecture (ISCA-27), June 2000.
  Abstract

1999

• The Use of Multithreading for Exception Handling
  Craig B. Zilles, Joel S. Emer, and Gurindar S. Sohi
  32nd International Symposium on Microarchitecture (MICRO-32), Nov 1999.
  Abstract

• Improving Virtual Function Call Target Prediction via Dependence-Based Pre-Computation
  Amir Roth, Andreas Moshovos and Gurindar S. Sohi
  International Conference on Supercomputing (ICS), June 20-25, 1999.
  Abstract

• Effective Jump-Pointer Prefetching for Linked Data Structures
  Amir Roth and Gurindar S. Sohi
  26th International Symposium on Computer Architecture (ISCA-25), May 2-4 1999.
  Abstract

1998

• Understanding the Differences Between Value Prediction and Instruction Reuse
  Avinash Sodani and Gurindar S. Sohi
  31st International Symposium on Microarchitecture (MICRO-31), Nov-Dec 1998.
  Abstract

• Task Selection for a Multiscalar Processor
  T.N. Vijaykumar and Gurindar S. Sohi
  31st International Symposium on Microarchitecture (MICRO-31), Nov-Dec 1998.
  Abstract

• Dependence Based Prefetching for Linked Data Structures
  Amir Roth, Andreas Moshovos, and Gurindar S. Sohi
  8th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), Oct 1998.
  Abstract

• An Empirical Analysis of Instruction Repetition
  Avinash Sodani and Gurindar S. Sohi
  8th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-VIII), Oct 1998.
  Abstract

• Modeling Program Predictability
  Yiannakis Sazeides and James E. Smith
  25th International Symposium on Computer Architecture (ISCA-25), June-July 1998.
  Abstract

• Exploitation Idle Floating-Point Resources for Integer Execution
  S. Subramanya Sastry, Subbarao Palacharla, and Jim Smith
  SIGPLAN '98 Conference on Programming Language Design and Implementation (PLDI), 1998.
  Abstract

• Speculative Versioning Cache
  Sridhar Gopal, T.N. Vijaykumar, J. E. Smith and G. S. Sohi
  Fourth International Symposium on High-Performance Computer Architecture (HPCA-4), Feb 1998.
  Abstract Technical report

1997

• Exploiting Dead Value Information
  Milo M. Martin, Amir Roth, Charles N. Fischer
  30th Annual international Symposium on Microarchitecture (MICRO-30), Dec 1997.
  Abstract

• Streamlining Inter-operation Memory Communication via Data Dependence Prediction
  Andreas Moshovos and Gurindar S. Sohi
  30th Annual international Symposium on Microarchitecture (MICRO-30), Dec 1997.
  Abstract

• Path-Based Next Trace Prediction
  Quinn Jacobson, Eric Rotenberg and James E. Smith
  30th Annual international Symposium on Microarchitecture (MICRO-30), Dec 1997.
  Abstract

• The Predictability of Data Values
  Yiannakis Sazeides and James E. Smith
  30th Annual international Symposium on Microarchitecture (MICRO-30), Dec 1997.
  Abstract

• Trace Processors
  Eric Rotenberg, Quinn Jacobson, Yiannakis Sazeides, Jim Smith
  30th Annual international Symposium on Microarchitecture (MICRO-30), Dec 1997.
  Abstract

• Dynamic Speculation and Synchronization of Data Dependences
  Andreas I. Moshovos, Scott E. Breach, T.N. Vijaykumar, Gurindar S. Sohi
  24th International Symposium on Computer Architecture (ISCA-24), June 1997.
  Abstract

• Dynamic Instruction Reuse
  Avinash Sodani and Gurindar S. Sohi
  24th International Symposium on Computer Architecture (ISCA-24), June 1997.
  Abstract

• Complexity-Effective Superscalar Processors
  Subbarao Palacharla, Norman P. Jouppi, James E. Smith
  24th International Symposium on Computer Architecture (ISCA-24), June 1997.
  Abstract Technical report

• Control Flow Speculation in Multiscalar Processors
  Quinn Jacobson, Steve Bennett, Nikhil Sharma, J. E. Smith
  Third International Symposium on High-Performance Computer Architecure (HPCA-3), Feb 1997.
  Abstract

• Register Communication Strategies for the Multiscalar Architecture
  T. N. Vijaykumar, S. E. Breach and G. S. Sohi
  Technical Report #1333, Computer Sciences Department, University of Wisconsin-Madison, February 1997.
  

1996

• The Performance Potential of Data Dependence Speculation & Collapsing
  Yiannakis Sazeides, Stamatis Vassiliadis, J. E. Smith
  29th International Symposium on Microarchitecture (MICRO-29), Dec 1996.
  Abstract

• Assigning Confidence to Conditional Branch Predictions
  Erik Jacobsen, Eric Rotenberg, J. E. Smith
  29th International Symposium on Microarchitecture (MICRO-29), Dec 1996.
  Abstract

• Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching
  Eric Rotenberg, Steve Bennett, J. E. Smith
  29th International Symposium on Microarchitecture (MICRO-29), Dec 1996.
  Abstract Technical report

• Data Memory Alternatives for Multiscalar Processors
  S. E. Breach, T. N. Vijaykumar, Sridhar Gopal J. E. Smith and G. S. Sohi
  Technical Report #1344, Computer Sciences Department, University of Wisconsin-Madison, November 1996.
  

• High-Bandwidth Address Translation for Multiple-Issue Processors
  T. M. Austin and G. S. Sohi
  23rd Annual International Symposium on Computer Architecture (ISCA-23), May 1996.
  Abstract

• ARB: A Hardware Mechanism for Dynamic Reordering of Memory References
  M. Franklin and G. S. Sohi
  IEEE Transactions on Computers, May 1996.
  Abstract

• A Dynamic Approach to Improve the Accuracy of Data Speculation
  A. I. Moshovos, S. E. Breach, T. N. Vijaykumar and G. S. Sohi
  Technical Report #1316, Computer Sciences Department, University of Wisconsin-Madison, March 1996.
  

1995

• The Microarchitecture of Superscalar Processors
  J. E. Smith and G. S. Sohi
  Proceedings of the IEEE, December 1995.
  Abstract

• Zero-Cycle Loads: Microarchitecture Support for Reducing Load Latency
  T. M. Austin and G. S. Sohi
  28th Annual International Symposium on Microarchitecture (MICRO-28), 1995.
  Abstract

• Multiscalar Processors
  G. S. Sohi, S. Breach, and T. N. Vijaykumar
  22th International Symposium on Computer Architecture (ISCA-22), 1995.
  Abstract

• Streamlining Data Cache Access with Fast Address Calculation
  T. M. Austin, D. N. Pnevmatikatos, and G. S. Sohi
  22th International Symposium on Computer Architecture (ISCA-22), 1995.
  Abstract

1994

• The Anatomy of the Register File in a Multiscalar Processor
  S. Breach, T. N. Vijaykumar, and G. S. Sohi
  27th Annual International Symposium on Microarchitecture (MICRO-27), 1994.
  Abstract

• Request Combining in Multiprocessors with Arbitrary Interconnection Networks
  A. Lebeck and G. S. Sohi
  in IEEE Transactions on Parallel and Distributed Systems, 1994.
  

• Efficient Detection of All Pointer and Array Access Errors
  T. M. Austin, S. E. Breach and G. S. Sohi
  SIGPLAN '94 Conference on Programming Language Design and Implementation, 1994.
  Abstract Technical report

• Guarded Execution and Branch Prediction in Dynamic ILP Processors
  D. Pnevmatikatos and G. S. Sohi
  21th International Symposium on Computer Architecture (ISCA-21), 1994.
  Abstract Technical Report

1993

• Memory Systems
  J. R. Goodman and G. S. Sohi
  The Handbook of Electrical Engineering, CRC Press, 1993.
  

• Control Flow Prediction for Dynamic ILP Processors
  D. Pnevmatikatos, M. Franklin and G. S. Sohi
  26th Annual International Symposium on Microarchitecture (MICRO-26), 1993.
  Abstract

• Knapsack: A Zero-Cycle Memory Hierarchy Component
  T. M. Austin, T. N. Vijaykumar, and G. S. Sohi
  Technical Report #1189, Computer Sciences Department, University of Wisconsin-Madison, November 1993.
  

• Tetra: Evaluation of Serial Program Performance on Fine-Grain Parallel Processors
  T. M. Austin and G. S. Sohi
  Technical Report #1162, Computer Sciences Department, University of Wisconsin-Madison, July 1993.
  

1992

• Register Traffic Analysis for Streamlining Inter-operation Communication in Fine-Grain Parallel Processors
  M. Franklin and G. S. Sohi
  25th Annual International Symposium on Microarchitecture (MICRO-25), 1992.
  Abstract

• The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism
  M. Franklin and G. S. Sohi
  19th International Symposium on Computer Architecture (ISCA-19), 1992.
  Abstract

• Dynamic Dependency Analysis of Ordinary Programs
  T.M. Austin and G. S. Sohi
  19th International Symposium on Computer Architecture (ISCA-19), 1992.
  Abstract

Theses

Jichaun Chang, Ph.D., August 2007, PDF Cooperative Caching for Chip Multiprocessors


Saisanthosh Balakrishnan, Ph.D., June 2007, PDF Program Demultiplexing: Data-flow Based Speculative Parallelization of Methods in Sequential Programs


Adam Butts, Ph.D., December 2004, PDF Optimizing Inter-Instruction Value Communication through Degree of Use Prediction


Craig Zilles, Ph.D., August 2002, PDF Postscript Master/Slave Speculative Parallellization and Approximate Code


Amir Roth, Ph.D., August 2001, PDF Postscript Pre-Execution via Speculative Data-Driven Multithreading


Avinash Sodani, Ph.D., April 2000, Postscript Dynamic Instruction Reuse


Andreas Moshovos, Ph.D., December 1998, PDF Memory Dependence Prediction


Scott Breach, Ph.D., December 1998, PDF Postscript The Design and Evaluation of Multiscalar Processors


Subbarao Palacharla, Ph.D., February 1998, PDF Postscript Complexity-Effective Superscalar Processors


T. N. Vijaykumar, Ph.D., January 1998, PDF Postscript Compiling for the Multiscalar Architecture


Todd Austin, Ph.D., April 1996, PDF Postscript Hardware and Software Mechanisms for Reducing Load Latency


Dionisios Pnevmatikatos, Ph.D., December 1995, PDF Postscript Incorporating Guarded Execution into Existing Instruction Sets


Manoj Franklin, Ph.D., December 1993, PDF Postscript The Multiscalar Architecture


Mark Friedman, Ph.D., January 1992, PDF Postscript An Architectural Characterization of Prolog Execution


Sriram Vajapeyam, Ph.D., December 1991, PDF Postscript Instruction Level Characterization of the Cray Y-MP Processor


Men-Chow Chiang, Ph.D., September 1991, PDF Postscript Memory System Design for Bus Based Multiprocessors


Padmaja Nandula, M.S., August 1998, PDF Postscript Synthesis of Kestrel Multiscalar Processor


Selim Bilgin, M.S., May 1997, PDF Postscript Incorporating Guard Instructions into Existing Architectures

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