TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP

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Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Nitya Ranganathan, Doug Burger, Stephen W. Keckler, Robert G. McDonald, and Charles R. Moore. TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP. ACM Transactions on Architecture and Code Optimization(TACO), 1(1):62-93, March 2004.

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Abstract

This article describes the polymorphous TRIPS architecture which canbe configured for different granularities and types of parallelism.The TRIPS architecture is the first in a class of post-RISC,dataflow-like instruction sets called Explicit Data-Graph Execution(EDGE). This EDGE ISA is coupled with hardware mechanisms that enablethe processing cores and the on-chip memory system to be configuredand combined in different modes for instruction, data, or thread-levelparallelism. To adapt to small and large-grain concurrency, the TRIPSarchitecture prototype contains two out-of-order, 16-wide-issue GridProcessor cores, which can be partitioned when easily extractablefine-grained parallelism exists. This approach to polymorphismprovides better performance across a wide range of application typesthan an approach in which many small processors are aggregated to runworkloads with irregular parallelism. Our results show that highperformance can be obtained in each of the three modes--ILP, TLP, andDLP--demonstrating the viability of the polymorphous coarse-grainedapproach for future microprocessors.

Additional Information

This is a test of the extra info broadcasting system.

BibTeX

 @Article{taco2004,
   author = "Karthikeyan Sankaralingam and Ramadass Nagarajan and Haiming Liu and Changkyu Kim and Jaehyuk Huh and Nitya Ranganathan and Doug Burger and Stephen W. Keckler and Robert G. McDonald and Charles R. Moore",
   title =     "{TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP}",
   journal =      "ACM Transactions on Architecture and Code Optimization(TACO)",
   volume = "1",
   number = "1",
   year =         {2004},
   pages = "62-93",
   month = "March",
   abstract={
 This article describes the polymorphous TRIPS architecture which can
 be configured for different granularities and types of parallelism.
 The TRIPS architecture is the first in a class of post-RISC,
 dataflow-like instruction sets called Explicit Data-Graph Execution
 (EDGE).  This EDGE ISA is coupled with hardware mechanisms that enable
 the processing cores and the on-chip memory system to be configured
 and combined in different modes for instruction, data, or thread-level
 parallelism. To adapt to small and large-grain concurrency, the TRIPS
 architecture prototype contains two out-of-order, 16-wide-issue Grid
 Processor cores, which can be partitioned when easily extractable
 fine-grained parallelism exists.  This approach to polymorphism
 provides better performance across a wide range of application types
 than an approach in which many small processors are aggregated to run
 workloads with irregular parallelism. Our results show that high
 performance can be obtained in each of the three modes--ILP, TLP, and
 DLP--demonstrating the viability of the polymorphous coarse-grained
 approach for future microprocessors.
  },
   bib_dl = "http://portal.acm.org/citation.cfm?id=980152.980156&coll=portal&dl=ACM&idx=980152&part=periodical&WantType=periodical&title=ACM Transactions on Architecture and Code Optimization (TACO)&CFID=20737705&CFTOKEN=20887410",
   bib_pubtype = {Journal},
   bib_rescat = {proj-trips},
   bib_extra_info = {This is a test of the extra info broadcasting system.}
 }

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