Design and Implementation of the PLUG Architecture for Programmable and Efficient Network Lookups

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Amit Kumar, Lorenzo De Carli, Sung Jim Kim, Marc de Kruijf, Karthikeyan Sankaralingam, Cristian Estan, and Somesh Jha. Design and Implementation of the PLUG Architecture for Programmable and Efficient Network Lookups. In Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques (PACT), 2010.

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Abstract

This paper proposes a new architecture called Pipelined LookUp Grid(PLUG) that can perform data structure lookups in networkprocessing. PLUGs are programmable and through simplicity achievepower efficiency. We draw upon the insights that data structurelookups have natural structure that can be statically determined andexploited. The PLUG execution model transforms data-structure lookupsinto pipelined stages of computation and associates small code-blockswith data. The PLUG architecture is a tiled architecture with eachtile consisting predominantly of SRAMs, a lightweight no-bufferingrouter, and an array of lightweight computation cores. Using aprinciple of fixed delays in the execution model, the architecture iscontention-free and completely statically scheduled thus achievinghigh energy efficiency. The architecture enables rapid deployment ofnew network protocols and generalizes as a data-structure accelerator.This paper describes the PLUG architecture, the compiler, andevaluates our RTL prototype PLUG chip synthesized on a 55nm technologylibrary. We evaluate six diverse high-end network processing workloadsincluding IPv4, IPv6, and Ethernet forwarding. We show that at a 55nmtechnology, a 16-tile PLUG occupies 58 mm2, provides 4MB on-chipstorage, and sustains a clock frequency of 1 GHz. This translates to 1billion lookups per second, a latency of 18ns to 219ns, and averagepower less than 1 watt.

BibTeX

 @inproceedings{pact10:plug,
   author={Amit Kumar and Lorenzo De Carli and Sung Jim Kim and Marc de Kruijf and Karthikeyan Sankaralingam and Cristian Estan and Somesh Jha},
   title={Design and Implementation of the PLUG Architecture for Programmable and Efficient Network Lookups},
   booktitle="{Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques (PACT)}",
   year={2010},
   abstract = {
 This paper proposes a new architecture called Pipelined LookUp Grid
 (PLUG) that can perform data structure lookups in network
 processing. PLUGs are programmable and through simplicity achieve
 power efficiency. We draw upon the insights that data structure
 lookups have natural structure that can be statically determined and
 exploited. The PLUG execution model transforms data-structure lookups
 into pipelined stages of computation and associates small code-blocks
 with data. The PLUG architecture is a tiled architecture with each
 tile consisting predominantly of SRAMs, a lightweight no-buffering
 router, and an array of lightweight computation cores.  Using a
 principle of fixed delays in the execution model, the architecture is
 contention-free and completely statically scheduled thus achieving
 high energy efficiency. The architecture enables rapid deployment of
 new network protocols and generalizes as a data-structure accelerator.
 This paper describes the PLUG architecture, the compiler, and
 evaluates our RTL prototype PLUG chip synthesized on a 55nm technology
 library. We evaluate six diverse high-end network processing workloads
 including IPv4, IPv6, and Ethernet forwarding. We show that at a 55nm
 technology, a 16-tile PLUG occupies 58 mm2, provides 4MB on-chip
 storage, and sustains a clock frequency of 1 GHz. This translates to 1
 billion lookups per second, a latency of 18ns to 219ns, and average
 power less than 1 watt.
 },
   bib_dl_pdf = {http://www.cs.wisc.edu/vertical/papers/2010/pact10-plug.pdf},
   bib_dl_ppt = {http://www.cs.wisc.edu/vertical/talks/2010/pact10-plug.ppt},
   bib_pubtype = {Refereed Conference},
   bib_rescat = {proj-relax}
 }

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