Distributed Microarchitectural Protocols in the TRIPS Prototype Processor

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Karthikeyan Sankaralingam, Ramadass Nagarajan, Robert McDonald, Rajagopalan Desikan, Saurabh Drolia, M.S. Govindan andPaul Gratz, Divya Gulati, Heather Hanson andChangkyu Kim, Haiming Liu, Nitya Ranganathan andSimha Sethumadhavan, Sadia Sharif, Premkishore Shivakumar, Stephen W. Keckler, and Doug Burger. Distributed Microarchitectural Protocols in the TRIPS Prototype Processor. In Proceedings of the 39th Annual International Symposium on Microarchitecture, December 2006.

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Abstract

Growing on-chip wire delays will cause many future microarchitecturesto be distributed, in which hardware resources within a singleprocessor become nodes on one or more switched micronetworks. Sincelarge processor cores will require multiple clock cycles to traverse,control must be distributed, not centralized. This paper describes thecontrol protocols in the TRIPS processor, a distributed, tiledmicroarchitecture that supports dynamic out-of-order execution. Itdetails each of the five types of reused tiles that compose theprocessor, the control and data networks that connect them, and thedistributed microarchitectural protocols that implement instructionfetch, execution, flush, and commit. We also describe the physicaldesign issues that arose when implementing the microarchitecture in a170M transistor, 130nm ASIC prototype chip composed of two 16-wideissue distributed processor cores and a distributed 1MB non-uniform(NUCA) on-chip memory system.

Additional Information

This is a test of the extra info broadcasting system.

BibTeX

 @InProceedings{micro06:trips,
   author =       {Karthikeyan Sankaralingam and Ramadass Nagarajan and Robert McDonald
 and Rajagopalan Desikan and Saurabh Drolia and M.S. Govindan and
 Paul Gratz and Divya Gulati and Heather Hanson and
 Changkyu Kim and Haiming Liu and Nitya Ranganathan and
 Simha Sethumadhavan and Sadia Sharif and
 Premkishore Shivakumar and Stephen W. Keckler and Doug Burger},
   title =        "{Distributed Microarchitectural Protocols in the TRIPS Prototype Processor}",
   booktitle =    "Proceedings of the 39th Annual International Symposium on Microarchitecture",
   year =         2006,
   month =        {December},
   abstract={
 Growing on-chip wire delays will cause many future microarchitectures
 to be distributed, in which hardware resources within a single
 processor become nodes on one or more switched micronetworks. Since
 large processor cores will require multiple clock cycles to traverse,
 control must be distributed, not centralized. This paper describes the
 control protocols in the TRIPS processor, a distributed, tiled
 microarchitecture that supports dynamic out-of-order execution. It
 details each of the five types of reused tiles that compose the
 processor, the control and data networks that connect them, and the
 distributed microarchitectural protocols that implement instruction
 fetch, execution, flush, and commit. We also describe the physical
 design issues that arose when implementing the microarchitecture in a
 170M transistor, 130nm ASIC prototype chip composed of two 16-wide
 issue distributed processor cores and a distributed 1MB non-uniform
 (NUCA) on-chip memory system.  },
   bib_dl_pdf = "http://www.cs.wisc.edu/~karu/docs/papers/utexas/micro06-trips-proto.pdf",
   bib_pubtype = {Refereed Conference},
   bib_rescat = {proj-trips},
   bib_extra_info = {This is a test of the extra info broadcasting system.}
 }

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