Universal Mechanisms for Data-Parallel Architectures

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Karthikeyan Sankaralingam, Stephen W. Keckler, William R. Mark, and Doug Burger. Universal Mechanisms for Data-Parallel Architectures. In Proceedings of the 36th Annual International Symposium on Microarchitecture, pp. 303-314, December 2003.

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Abstract

Data-parallel programs are both growing in importanceand increasing in diversity, resulting in specialized processors targeted at specific classes of these programs. Thispaper presents a classification scheme for data-parallel programattributes, and proposes micro-architectural mechanisms to supportapplications with diverse behavior using a single reconfigurablearchitecture.We focus on the following four broad kinds of data-parallel programs--- DSP/multimedia, scientific, networking, and real-time graphicsworkloads. While all of these programs exhibit high computationalintensity, coarse-grain regular control behavior, and some regularmemory access behavior, they show wide variance in the computationrequirements, fine grain control behavior, and the frequency of othertypes of memory accesses. Based on this study of applicationattributes, this paper proposes a set of general micro-architecturalmechanisms that enable a baseline architecture to be dynamicallytailored to the demands of a particular application. These mechanismsprovide efficient execution across a spectrum of data-parallelapplications and can be applied to diverse architectures ranging fromvector cores to conventional superscalar cores. Our results using a baseline TRIPS processor show that the configurability of the architecture to theapplication demands provides harmonic mean performance improvement of5%--55% over scalable yet less flexible architectures, and performs competitively against specialized architectures.

Additional Information

This is a test of the extra info broadcasting system.

BibTeX

 @InProceedings{micro03,
   author =       "Karthikeyan Sankaralingam and Stephen W. Keckler and William R. Mark and Doug Burger",
   title =        "{Universal Mechanisms for Data-Parallel Architectures}",
   booktitle =    "Proceedings of the 36th Annual International Symposium on Microarchitecture",
   year =         2003,
   pages = "303-314",
   month =        {December},
   abstract={Data-parallel programs are both growing in importance
 and increasing in diversity, resulting in
 specialized processors
 targeted at specific classes of these programs. This
 paper presents a classification scheme for data-parallel program
 attributes, and proposes micro-architectural mechanisms to support
 applications with diverse behavior using a single reconfigurable
 architecture.
 We focus on the following four broad kinds of data-parallel programs
 --- DSP/multimedia, scientific, networking, and real-time graphics
 workloads.  While all of these programs exhibit high computational
 intensity, coarse-grain regular control behavior, and some regular
 memory access behavior, they show wide variance in the computation
 requirements, fine grain control behavior, and the frequency of other
 types of memory accesses. Based on this study of application
 attributes, this paper proposes a set of general micro-architectural
 mechanisms that enable a baseline architecture to be dynamically
 tailored to the demands of a particular application. These mechanisms
 provide efficient execution across a spectrum of data-parallel
 applications and can be applied to diverse architectures ranging from
 vector cores to conventional superscalar cores. Our results using a baseline TRIPS processor show that the configurability of the architecture to the
 application demands provides harmonic mean performance improvement of
 5\%--55\% over scalable yet less flexible architectures, and performs competitively against specialized architectures.
 },
   bib_dl_pdf = "http://www.cs.wisc.edu/~karu/docs/papers/utexas/micro03-dlp.pdf",
   bib_pubtype = {Refereed Conference},
   bib_rescat = {proj-trips},
   bib_extra_info = {This is a test of the extra info broadcasting system.}
 }

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