A Design Space Evaluation of Grid Processor Architectures

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Ramadass Nagarajan, Karthikeyan Sankaralingam, Stephen W. Keckler, and Doug Burger. A Design Space Evaluation of Grid Processor Architectures. In Proceedings of the 34th Annual International Symposium on Microarchitecture, pp. 40-51, December 2001.
Won Robert P. Hamilton best paper award 2001.

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Abstract

In this paper, we survey the design space of a new class ofarchitectures called Grid Processor Architectures (GPAs).These architectures are designed to scale with technology, allowingfaster clock rates than conventional architectures while providingsuperior instruction-level parallelism on traditional workloadsand high performance across a range of application classes. A GPAconsists of an array of ALUs, each with limited control, connected bya thin operand network. Programs are executed by mapping blocks ofstatically scheduled instructions to the ALU array and executing themdynamically in dataflow order. This organization enables the criticalpaths of instruction blocks to be executed on chains of ALUs withouttransmitting temporary values back to the register file, avoiding mostof the large, unscalable structures that limit the scalability ofconventional architectures. Finally, we present simulation results ofa preliminary design, the GPA-1. With a half-cycle routing delay, weobtain performance roughly equal to an ideal 8-way, 512-entry windowsuperscalar core. With no inter-ALU delay, perfect memory, andperfect branch prediction, the IPC of the GPA-1 is more than twicethat of the ideal superscalar core, achieving an average of 11 IPCacross nine SPEC CPU2000 and Mediabench benchmarks.

Additional Information

This is a test of the extra info broadcasting system.

BibTeX

 @InProceedings{micro01,
   author =       "Ramadass Nagarajan and Karthikeyan Sankaralingam and Stephen W. Keckler and Doug Burger",
   title =        "{A Design Space Evaluation of Grid Processor Architectures}",
   pages =        {40--51},
   booktitle =    "Proceedings of the 34th Annual International Symposium on Microarchitecture",
   year =         2001,
   month =        {December},
   abstract={In this paper, we survey the design space of a new class of
 architectures called Grid Processor Architectures (GPAs).
 These architectures are designed to scale with technology, allowing
 faster clock rates than conventional architectures while providing
 superior instruction-level parallelism on traditional workloads
 and high performance across a range of application classes.  A GPA
 consists of an array of ALUs, each with limited control, connected by
 a thin operand network.  Programs are executed by mapping blocks of
 statically scheduled instructions to the ALU array and executing them
 dynamically in dataflow order.  This organization enables the critical
 paths of instruction blocks to be executed on chains of ALUs without
 transmitting temporary values back to the register file, avoiding most
 of the large, unscalable structures that limit the scalability of
 conventional architectures.  Finally, we present simulation results of
 a preliminary design, the GPA-1.  With a half-cycle routing delay, we
 obtain performance roughly equal to an ideal 8-way, 512-entry window
 superscalar core.  With no inter-ALU delay, perfect memory, and
 perfect branch prediction, the IPC of the GPA-1 is more than twice
 that of the ideal superscalar core, achieving an average of 11 IPC
 across nine SPEC CPU2000 and Mediabench benchmarks.},
   wwwnote =	 {Won <b>Robert P. Hamilton best paper award 2001.</b>},
   bib_dl_pdf = "http://www.cs.wisc.edu/~karu/docs/papers/utexas/micro01-grid.pdf",
   bib_pubtype = {Refereed Conference,Award Paper},
   bib_rescat = {proj-trips},
   bib_extra_info = {This is a test of the extra info broadcasting system.}
 }

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