A Fast and Highly Accurate Path Delay Emulation Framework for Logic-Emulation of Timing Speculation

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Shuou Nomura, Karthikeyan Sankaralingam, and Ranganathan Sankaralingam. A Fast and Highly Accurate Path Delay Emulation Framework for Logic-Emulation of Timing Speculation. In Proceedings of the 22nd International Test Conference (ITC), 2010.

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Abstract

This paper proposes a novel path-delay fault emulation techniquecalled Replay. We specifically show it allows FPGA emulation ofdigital ICs that adopt timing-speculation techniques. For eachflip-flop, Replay builds a timing-error predictor based on timingspeculationsâs aggressive clock period. We use a heuristic whichreplicates the combination logic and uses path delays to determinewhich paths will be excited based on the aggressive clock period. Thetiming-error prediction accuracy is more than 99% for a set of realworkloads on the OpenRISC processor and the FPGA emulation speed showspractically no slowdown. We also demonstrate that Replay can evaluatethe impact of voltage-drop timing-faults. This fast and accuratetiming-error prediction enables practical emulation oftiming-speculation and quantitative analysis early in thedesign-cycle.

BibTeX

 @inproceedings{itc10:replay,
   author={Shuou Nomura and Karthikeyan Sankaralingam and Ranganathan Sankaralingam},
   title={A Fast and Highly Accurate Path Delay Emulation Framework for Logic-Emulation of Timing Speculation},
   booktitle="{Proceedings of the 22nd International Test Conference (ITC)}",
   year={2010},
   abstract = {
 This paper proposes a novel path-delay fault emulation technique
 called Replay. We specifically show it allows FPGA emulation of
 digital ICs that adopt timing-speculation techniques. For each
 flip-flop, Replay builds a timing-error predictor based on timing
 speculationsâs aggressive clock period. We use a heuristic which
 replicates the combination logic and uses path delays to determine
 which paths will be excited based on the aggressive clock period. The
 timing-error prediction accuracy is more than 99% for a set of real
 workloads on the OpenRISC processor and the FPGA emulation speed shows
 practically no slowdown. We also demonstrate that Replay can evaluate
 the impact of voltage-drop timing-faults. This fast and accurate
 timing-error prediction enables practical emulation of
 timing-speculation and quantitative analysis early in the
 design-cycle.
 },
   bib_dl_pdf = {http://www.cs.wisc.edu/vertical/papers/2010/itc10-replay.pdf},
   bib_dl_ppt = {http://www.cs.wisc.edu/vertical/talks/2010/itc10-replay.pdf},
   bib_pubtype = {Refereed Conference},
   bib_rescat = {proj-relax}
 }

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