Toward a Multicore Architecture for Real-time Ray-tracing

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Venkatraman Govindaraju, Peter Djeu, Karthikeyan Sankaralingam, Mary Vernon, and William R. Mark. Toward a Multicore Architecture for Real-time Ray-tracing. In Proceedings of the 41st Annual International Symposium on Microarchitecture, MICRO, November 2008.
Co-winner of Best student presentation award. MICRO 2008.

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Abstract

Significant improvement to visual quality for real-time 3D graphics requires modeling of complex illumination effects like soft-shadows, reflections, and diffuse lighting interactions. The conventional Z-buffer algorithm driven GPU model does not provide sufficient support for this improvement. This paper targets the entire graphics system stack and demonstrates algorithms, a software architecture, and a hardware architecture for real-time rendering with a paradigm shift to ray-tracing. The three unique features of our system called Copernicus are support fo r dynamic scenes, high image quality, and execution on programmable multicore architectures. The focus of this paper is the synergy and interaction between applications, architecture, and evaluation. First, we describe the ray-tracing algorithms which are designed to use redundancy and partitioning to achieve locality. Second, we describe the architecture which uses ISA specialization, multi-threading to hide memory delays and supports only local coherence. Finally, we develop an analytical performance model for our 128-core system, using measurements from simulation and a scaled-down prototype system. More generally, this paper addresses an important issue of mechanisms and evaluation for challenging workloads for future processors. Our results show that a single 8-core tile (each core 4-way multithreaded) can be almost 100% utilized and sustain 10 million rays/second. Sixteen such tiles, which can fit on a 240$mm^2$ chip in 22nm technology, make up the system and with our anticipated improvements in algorithms, can sustain real-time rendering. The mechanisms and the architecture can potentially support other domains like irregular scientific computations and physics computations.

BibTeX

 @inproceedings{micro2008:raytrace,
  author =       {Venkatraman Govindaraju and Peter Djeu and Karthikeyan Sankaralingam and Mary Vernon and William R. Mark},
  title =        "{Toward a Multicore Architecture for Real-time Ray-tracing}",
  booktitle =    "{Proceedings of the 41st Annual International Symposium on Microarchitecture, MICRO}",
  year =         2008,
  month =        {November},
  abstract = {
 Significant improvement to visual quality for real-time 3D
 graphics requires modeling of complex illumination effects like
 soft-shadows, reflections, and diffuse lighting interactions. The
 conventional Z-buffer algorithm driven GPU model does not provide
 sufficient support for this improvement. This paper targets the
 entire graphics system stack and demonstrates algorithms, a
 software architecture, and a hardware architecture for real-time
 rendering with a paradigm shift to ray-tracing. The three unique
 features of our system called Copernicus are support fo r
 dynamic scenes, high image quality, and execution
 on programmable multicore architectures. The focus of this paper
 is the synergy and interaction between applications, architecture,
 and evaluation. First, we describe the ray-tracing algorithms
 which are designed to use redundancy and partitioning to achieve
 locality. Second, we describe the architecture which uses ISA
 specialization, multi-threading to hide memory delays and supports
 only local coherence. Finally, we develop an analytical
 performance model for our 128-core system, using measurements from
 simulation and a scaled-down prototype system. More generally,
 this paper addresses an important issue of mechanisms and
 evaluation for challenging workloads for future processors. Our
 results show that a single 8-core tile (each core 4-way
 multithreaded) can be almost 100\% utilized and sustain 10 million
 rays/second. Sixteen such tiles, which can fit on a 240$mm^2$ chip
 in 22nm technology, make up the system and with our anticipated
 improvements in algorithms, can sustain real-time rendering. The
 mechanisms and the architecture can potentially support other
 domains like irregular scientific computations and physics
 computations.},
  bib_dl_pdf = {http://www.cs.wisc.edu/vertical/papers/2008/micro08-copernicus.pdf},
  bib_dl_ppt = {http://www.cs.wisc.edu/vertical/talks/2008/micro08-copernicus.pdf},
  bib_pubtype = {Refereed Conference},
  bib_rescat = {Architecture}
  wwwnote =      {<b>Co-winner of Best student presentation award. MICRO 2008.</b>},
 }

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