High-end routers and switches perform performance-critical lookups into large data based on network packet content. Current designs rely on specialized hardware modules for high performance. While mostly sufficient, emerging new protocols create a problem. For them to be deployed, expensive equipment upgrades are required for each protocol. To support the rapid deployment of new data plane protocols, we are investigating the PLUG system which includes a programming model, compiler, and architecture. This project seeks to develop a unified framework for future network devices with four components: a) an abstract execution model to represent hardware, b) a toolchain to ease implementation, d) quantitative performance evaluation of protocols, and d) programmable hardware architectures specialized for the core operations in network protocols.
Stay tuned, more to appear soon:
- PLUG runtime and compiler
- PLUG reference applications (Ethernet forwarding, IPv4, IPv6, Seattle, Ethane, DFA Matching :)
- PLUG simulator
- Our SIGCOMM paper
This project is co-led by Karu Sankaralingam, Somesh Jha, and Cristian Estan.