DySER

Hardware specialization with DySER

The DySER project complements our Idempotence project in looking at ways to complement the core and specialize it in various ways based on the underlying workload. Our DySER prototype RTL design and compiler should be available for download soon. The motivation for DySER was our early work on building a specialized multi-core architecture for ray tracing.

• DySER: Unifying Functionality and Parallelism Specialization for Energy Efficient Computing, IEEE Micro to appear September 2012. IEEE Xplore preprint
• DySER+OpenSPARC Prototype. In 38th Annual Asilomar Microcomputer Workshop (AMW), April 2012. Slides from talk
• Design, Integration, and Implementation of the DySER Hardware Accelerator into OpenSPARC, HPCA 2012, pdf
• Dynamically Specialized Datapaths for Energy Efficient Computing, HPCA 2011, pdf
• Toward A Multicore Architecture for Real-time Raytracing, MICRO-41, 2008, pdf

DySER opensource project wiki:
http://research.cs.wisc.edu/vertical/dyser-release-v1/doku.php