PlanAhead Projects

There are two planAhead projects that serve as a starting point for testing (ZedBoard101) and PERSim's Input Sequence Extraction and Fault Injection mechanisms (XilinxProject).
planAhead [projectname.ppr] opens these projects.

OpenRISC Verilog

The OpenRISC RTL used in PERSim was downloaded in November 2012. The entire RTL used is located in XilinxProject/zed_first_custom_hw.srcs/sources_1/edk/proc_system/pcores/or1200_fpga_top_v1_00_a/hdl/verilog/*.v. The or1200_defines.v file is tweaked to target Xilinx FPGAs (registers use Xilinx BRAMs etc.,). The only other modification made are hacks to tap signals for input sequence extraction and fault injection. or1200_cpu.v includes instantiations of modules that support these mechanisms.

Hypervisor

Also in the OpenRISC directory, the user_logic.v file contains the hardware part of the hypervisor. The the OpenRISC core is instantiated in this file as well. At the core, this top level module contains 32 32-bit registers that hold several control and status values.

Software

Both input sequence extraction and fault injection and deterministic re-execution are handled in XilinxProject/zed_first_custom_hw.sdk/SDK/SDK_Export/hello_world_0/src/helloworld.c. This file first defines the benchmark executed, the main() PC and exit PCs. For each test, it copies the code to the OpenRISC memory, configures hypervisor registers accordingly and deasserts reset. It checks for program progress, and when done, reads out input sequences, architectural states etc., The output is printed out through UART to the host serial monitor.

OpenRISC binaries

The folder OpenRISC_Binaries contains .bin files and .dump files for each benchmark. The executable bin2h converts the .bin files to .h files that are then used by the hypervisor firmware.

Helper Scripts

We used several scripts (*.py files) to help speed up our tests. Unfortunately, these are not well documented. Please help us by improving/documenting/re-writing the scripts that you use.

Synthesis

For delay aware simulation, we synthesized the OpenRISC RTL targetting the 32-nm Synopsys library. Delay_Aware/synthesis/ contains .tcl scripts to synthesize and the or1200_cpu.syn.v which is the synthesized netlist. Please modify the .tcl file to point to your libraries.

Delay Aware Simulation

The delay aware simulation uses the 32-nm library as well. We use Synopsys VCS for our delay aware simulation. The scripts to compile and run vcs may be found in Delay_Aware/simulation.