PERSim has support to introduce faults in 72 fault sites spread over 10 gate chains. Adding fault sites requires you to extract the gates around a site to create the sub-circuit for delay aware simulation, modify the OpenRISC to extract input sequences and fault injectiona and the hypervisor software to read out the corresponding memories.

Delay Aware Simulation

If you have a particular gate or a module in mind, locate it in the synthesized netlist. Else pick a gate at random. Extract the gates around this gate till you hit flip-flops on the fan-in and fan-out. Make sure all these gates are connected. Save them as path.v. Add inputs and outputs similar to path.v in the path_x folders.

HINT : In our examples, we use only the critical paths. This is an approximation, a delay fault will first be seen in the critical path. We have ignored the other paths, hence, we have not captured the full impact of a delay fault. On the other hand, with higher detail (the more the number of gates) in the circuit, input sequence bit width increases.

Input Sequence Extraction

List the inputs in the path.v file you created for delay aware simulation. Locate the corresponding signals in the OpenRISC CPU RTL. In the or1200_cpu.v file, the or1200_trace_checker module saves the input sequences in memories. Make the necessary edits to connect the input sequences to new memories - similar to the ones already connected.

Fault injection and re-execution

Make edits similar to the input sequence extraction. Once done, re-synthesize to get a new .bit file in the ISE and planAhead IDE.

Chipscope is a debugging tool that lets you observe select signal states for about a 1000 cycle window. You can set triggers on when this window is sampled and displayed. We use Chipscope extensively after each modification. Search for instantiations of or1200_chipscope_if to see how this module is instantiated.

The source code for SPEC benchmarks that are modified may be found at OpenRISC/SpecModified/. We have modified and complied most of these benchmarks (see paper for details).

While OpenRISC is capable of compiling and running full unmodified programs, a few changes have to made to make them compatible with PERSim. This is due to the fact that PERSim has a limited memory footprint and that we avoid running Linux to ensure determinism.

The utils folder contains python scripts that help make the following changes.

Running bare-metal

As we run our benchmarks bare-metal, we remove all system calls and file I/Os. The following changes are necessary

  • Convert all input files and output files to integer arrays. bin2h in the utils directory converts any input file in an integer header.
  • All file opens are replaced by fmemopen which takes in the array we created as its inputs.
  • Comment out printfs. This is not mandatory, but helpful - the UART runs asynchronously and may cause indeterminism when a program is run multiple times.

Compiling

  • Compile : or32-elf-gcc -o [benchmark]_or32.o *.c
  • Create the dump file : or32-elf-objdump -D benchmark_or32.o benchmark_or32.dump
  • And the object file : or32-elf-objcopy --strip-all -O binary benchmark_or32.o benchmark_or32.bin
Make sure you run or1ksim with your complied code to make sure that it runs fine.

Our fault modeling mechanism concentrates on individual gates. In any given cycle, the delay aware simulation picks up on faults on this gate only. We do not model the interaction of faults - for example, if a particle strike may affect multiple gates around this gate.

We would love to get your help on improving PERSim. In particular, here are a few areas we believe we should improve upon in the short term.

ORPSoC (Linux)

We use OpenRISC standalone. Typical FPGA implementations include basic peripherals such as tick timers, UART etc., which are essential for OpenRISC to run Linux. We stripped these out

UART

Program progress is tracked by tracking the PC. There is limited support for reading out the printfs that are output on the UART. We would really appreciate it if you could make this interface robust. See UART_*.v and user_logic.v for the current implementation.

Benchmarks

SPEC2006, Parsec, Parboil etc., Remember the benchmarks must be re-written to run bare-metal and should have a memory footprint of less than 256MB.