Architecture-level

If you technique involves adding logic/hardware, begin by coding it up in Verilog. or1200_cpu.v is a good place to instantiate core level modules. or1200_wrapped.v is the top level that covers the CPU, Caches, TLBs etc., Once you have you module in place,

  • Modify the template Delay_Aware/Synthesis/synth.scr to include your module file and synthesize. You can obtain the change in area and power.
  • If necessary, add registers in the hypervisor and modify the firmware. Do this only if you need control over when your module is used - during the course of a test. Re-synthesize the FPGA implementation.
  • The input sequence extraction step typically does not change unless you make modifications to the circuit or program flow. Repeat the Fault Injection and re-execution with an without the module to see its impact.

Microarchitecture-level

If the idea targets specific paths, the effects are best observed in the delay aware simulation. In our experiments, we have used scripts that automatically identify paths based on their timing characteristics and modifies them. You can use the synthesis scripts (like in the architectural level techniques) to analyze area and power impact.
Once the individual circuits around select fault sites are extracted, add the microarchitectural changes as proposed. Analyze the changes in the delay aware simulation results to test the effectiveness of your technique.

Transistor or Gate-level ideas

Again, Delay aware simulation is the best place to implement gate level modifications. However, please change the behavior of the gates (in libaries) or add gates to the libaries. You may also find it useful to model the gates in Spice. As an example Fault_Modeling/Wearout/mosfetmodels.sp includes three variations of NMOS and PMOS transistors used in one our evaluations. While it is not straightforward to add a new type of gate to synthesis, modifying an existing gate is.

In addition to area and power/energy consumption, we have evaluated prediction horizon and time to predict for failure prediction mechanisms, detection latency for detection mechanisms, observed fault/error rates and occurrence patterns in flip flops, architectural state etc., Here are a few standard metrics.

Area, Power

Delay_Aware/Synthesis/ includes synthesis scripts that also report the area and energy consumption of circuits. We use the 32nm Synopsys library.

Performance

The hypervisor hardware user_logic.v contains cycle and instruction counters that can be triggered either at the start of each benchmark run or when the main() function is called. These may be used to measure CPI.

Reliability Metrics

The delay aware simulation outputs timing errors leading to logic faults on a cycle-by-cycle basis. The fault injection experiment can be used to output architectural (PC, register writes, LSU commits etc.,) error occurrence patters. Together these vectors can then be used to obtain metrics such as prediction horizon, time to predict, detection latency etc.,