A framework that lets you model reliability physics at the device level and study its impact on applications.
Our paper about PERSim.
PERSim lets you model physical effects at the device/transistor/gate level and see its impact on programs running in a processor. By combining device level simulation and FPGA acceleration into one framework, you can model the effects accurately and run programs end-to-end.
Read more about PERSim in our HPCA paper.
The program runs on a processor that sits on an FPGA. Parts of the circuits are simuated with gate delays or in SPICE.
A single experiment in PERSim is done in four steps. We model the faults, augment gate level simulation with the models input. We run programs on an FPGA and extract the inputs that would feed the gate level simulation. And using fault vectors the simulation generates, we introduce faults in another FPGA run and see if they cause architectural errors.
PERSim is built around the OpenRISC processor. Its mapped on to a Zynq FPGA on a ZedBoard. We will be using this for accelerating out input sequence extraction and fault injection steps.
For fault modeling, we use industry tools or custom code where suitable. The OpenRISC toolchain comes in handy to compile new programs. You'll find a lot more about how to get these components and how to use them in the next pages.
The best overview of PERSim can be found in our HPCA paper. This website serves two purposes.