Microbench
MICROBENCH: Extremely Simple Microbenchmarks
The following is a collection of micro-benchmarks inspired by Measuring Experimental Error in Microprocessor Simulation Rajagopalan (Desikan, Doug Burger, and Stephen W. Keckler).
The github link is here: https://github.com/VerticalResearchGroup/microbench
Its intended purpose is in the validation of general purpose out-of-order cores, by targetting individual micro-architectural features or effects. The table below shows the benchmark name, and brief description of the intended architectural effect or behavior. Please note this is by no means an exhaustive collection of mechanisms in an OOO processor.
| Benchmark Type | Benchmark Codename | Description |
|---|---|---|
| Control | CCa | Always Branch |
| CCe | Alternating Control Flow -- Easy to predict with Patern Table | |
| CCh | Random Control Flow -- Impossible to predict | |
| CCh_st | Control with stores | |
| CCm | Control which "mostly" goes in one direction. (heavily biased) | |
| CCl | Control with large basic-blocks (potentially larger flush penalty) | |
| CRd | Recursive Control Flow -- 1000 Deep | |
| CRf | Recursive Control Flow -- Fibonacci | |
| CS1 | Switch Case Statement of Size 10-- Different Case Each Time | |
| CS3 | Switch Case Statement of Size 10 -- Different Case Every third Time | |
| Data Parallel | DP1d | Simple Data Parallel Loop -- Double Arithmatic |
| DP1f | Simple Data Parallel Loop -- Float Arithmatic | |
| DPcvt | Simple Data Parallel Loop -- Converts Between Double/Float Arithmatic | |
| DPT | Simple Data Parallel Loop -- Float Sin Computation | |
| DPTd | Simple Data Parallel Loop -- Double Sin Computation | |
| Execution | ED1 | Integer Execution -- Length 1 Dependency Chain each Loop |
| EF | Floating Execution -- 8 Independent computations Per Loop | |
| EI | Integer Execution -- 8 Independent Computations Per Loop | |
| EM1 | Integer Execution -- Length 1 Dependency Chain each Loop (with multiplies) | |
| EM5 | Integer Execution -- Length 5 Dependency Chain each Loop (with multiplies) | |
| Memory | MC | Generates Many Conflict Misses |
| MD | Data Cache Resident Linked List Traversal | |
| MI | 8 Streams of independent memory access, all cache resident. | |
| MIP | Many Instruction Cache Misses | |
| ML2 | L2 resident linked list traversal. | |
| Mlsq | Dependent Load Store Access | |
| MM | Non-Cache resident linked list traversal. | |
| Store Intense | STc | Repeatedly Store In Consective Addresses, L1 Cache Resident |
| (stresses WB buffer) | STL2 | Repeatedly Store In Consective Addresses, L2 Cache Resident |
| STL2b | Repeatedly Store In Consective Addresses, performs load every 512 stores) |