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Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture

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Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Stephen W. Keckler, Doug Burger, and Charles R. Moore. Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture. In Proceedings of the 30th Annual International Symposium on Computer Architecture, pp. 422-433, June 2003.

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Abstract

This paper describes the polymorphous TRIPS architecture whichcan be configured for different granularities and types ofparallelism. TRIPS contains mechanisms that enable the processingcores and the on-chip memory system to be configured and combined indifferent modes for instruction, data, or thread-level parallelism.To adapt to small and large-grain concurrency, the TRIPS architecturecontains four out-of-order, 16-wide-issue Grid Processor cores, whichcan be partitioned when easily extractable fine-grained parallelismexists. This approach to polymorphism provides better performanceacross a wide range of application types than an approach in whichmany small processors are aggregated to run workloads with irregularparallelism. Our results show that high performance can be obtained ineach of the three modes--ILP, TLP, and DLP--demonstrating theviability of the polymmorphous coarse-grained approach for futuremicroprocessors.

Additional Information

This is a test of the extra info broadcasting system.

BibTeX

 @InProceedings{isca03,
   author =       "Karthikeyan Sankaralingam and Ramadass Nagarajan and Haiming Liu and Changkyu Kim and Jaehyuk Huh and Stephen W. Keckler and Doug Burger and Charles R. Moore",
   title =        "{Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture}",
   booktitle =    "Proceedings of the 30th Annual International Symposium on Computer Architecture",
   pages =        {422-433},
   year =         2003,
   month =        {June},
   abstract={This paper describes the polymorphous TRIPS architecture which
 can be configured for different granularities and types of
 parallelism.  TRIPS contains mechanisms that enable the processing
 cores and the on-chip memory system to be configured and combined in
 different modes for instruction, data, or thread-level parallelism.
 To adapt to small and large-grain concurrency, the TRIPS architecture
 contains four out-of-order, 16-wide-issue Grid Processor cores, which
 can be partitioned when easily extractable fine-grained parallelism
 exists.  This approach to polymorphism provides better performance
 across a wide range of application types than an approach in which
 many small processors are aggregated to run workloads with irregular
 parallelism. Our results show that high performance can be obtained in
 each of the three modes--ILP, TLP, and DLP--demonstrating the
 viability of the polymmorphous coarse-grained approach for future
 microprocessors.},
   bib_dl_pdf = "http://www.cs.wisc.edu/~karu/docs/papers/utexas/isca03-trips.pdf",
   bib_pubtype = {Refereed Conference},
   bib_rescat = {TRIPS},
   bib_extra_info = {This is a test of the extra info broadcasting system.}
 }

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