Oct 24, 2017

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Projects

Overview

The research in the Vertical group spans VLSI technology to software and application analysis. Such an integrated approach is necessary to design future high performance systems. Our research focuses on future systems targeting a 2020 time-frame considering three broad directions:

  • Exposing hardware reliability
  • Rethinking processor microarchitecture
  • Hardware specialization

Driving much of our work is detailed technology models and analytical tools.




Exposing hardware reliability: Relaxed systems

Devices are becoming increasingly brittle, highly varying in their properties, and error-prone, leading to a fundamentally unpredictable hardware substrate. The model of hardware being correct all the time, on all regions of chip, and forever, becomes prohibitively expensive to maintain. Emerging new classes of applications are increasingly relying on probabilistic methods. They have an inherent tolerance for uncertainty, do not require hardware to be correct all the time, and this provides an opportunity to creatively utilize hardware. We are investigating ways to expose hardware reliability at the device level through layers of the system stack up to the application. We are building system software, architecture, and microarchitectural mechanisms that can scale to future technologies.

  • Sampling + DMR: Practical and Low-overhead Permanent Fault Detection, ISCA 2011, pdf
  • Exploring the Interaction Between Device Lifetime Reliability and Security Vulnerabilities. Computer Architecture Letters, 10, 2011.
  • Relax: An Architectural Framework for Software Recovery of Hardware Faults, ISCA 2010, pdf
  • A Fast and Highly Accurate Path Delay Emulation Framework for Logic-Emulation of Timing Speculation, ITC 2010, pdf
  • A Unified Model for Timing Speculation: Evaluating the Impact of Technology Scaling, CMOS Design Style, and Fault Recovery Mechanism. DSN 2010, pdf
  • Exploring the Synergy of Emerging Workloads and Silicon Reliability Trends. SELSE 2009

Revisiting microarchitecture: Idempotence

We are revisiting some of the fundamental principles of processor microarchitecture design in the light of energy and reliability becoming primary constraints. In the Idempotence project, we observe that the mathematical property of idempotence which allows an operation to be performed multiple times producing the same results provides a powerful and elegant way to radically simplify and eliminate many hardware structures.

  • iGPU: Exception Support and Speculative Execution on GPUs, ISCA 2012, pdf
  • Static Analysis and Compiler Implementation of Idempotent Processing, PLDI 2012, pdf
  • Idempotent Processor Architecture, MICRO 2011, pdf
  • Relax: An Architectural Framework for Software Recovery of Hardware Faults, ISCA 2010, pdf

Hardware specialization: DySER

The DySER project complements the Idempotence project in looking at ways to complement the core and specialize it various ways based on the underlying workload. Our DySER prototype RTL design and compiler should be available for download soon. The motivation for DySER was our early work on building a specialized multi-core architecture for ray tracing.

  • Design, Integration, and Implementation of the DySER Hardware Accelerator into OpenSPARC, HPCA 2012, pdf
  • Dynamically Specialized Datapaths for Energy Efficient Computing, HPCA 2011, pdf
  • Toward A Multicore Architecture for Real-time Raytracing, MICRO-41, 2008, pdf

DySER + OpenSPARC opensource project wiki


Technology models and formal tools

We build detailed analytical models and workload analysis to understand the constraints and limitations of existing systems and to project performance of future systems we explore.

  • Dark Silicon and the End of Multicore Scaling, ISCA 2011, pdf; IEEE Micro Top Picks 2012
  • Challenge Benchmarks That Must be Conquered to Sustain the GPU Revolution, EAMA 2011, pdf
  • A Unified Model for Timing Speculation: Evaluating the Impact of Technology Scaling, CMOS Design Style, and Fault Recovery Mechanism. DSN 2010, pdf
  • Evaluating GPUs for Network Packet Signature Matching, ISPASS 2009, pdf

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