• Protocols

Overview

SLICC protocols specify the entire memory system logic. Protocols are generally classified as SMP, CMP, or SCMP.

SMP protocols assume each node consists of a processor, private L1, private L2, and Memory/Directory controller. The SMP protocols can be used to model a CMP with private caches. Both the L1 and L2 caching is implemented in a single controller.

CMP protocols assume each node consists of processors with their private L1 caches, and a banked, shared L2 cache. The CMP protocols generally support Multiple-CMP systems unless otherwise noted. The L1 and L2 controllers are split.

SCMP protocols assume a Single-CMP with split L1 and L2 controllers.

1. MOSI_SMP_bcast

   • Description: A snooping, broadcast-based SMP cache coherence protocol and system. Each processor has a L1I, L1D, and unified L2 cache. The same SLICC controller is used for all caches (MOSI_SMP_bcast-cache.sm).

     Notes:

     • The network must be fully ordered with 2 virtual networks. Set g_NETWORK_TOPOLOGY to either HIERARCHICAL_SWITCH or CROSSBAR
2. MOESI_SMP_directory

   • Description: A directory-based SMP cache coherence protocol and system. Each processor has a L1I, L1D, and unified L2 cache. The same SLICC controller is used for all caches.

     Notes:

     • Three virtual networks required
3. MOESI_SMP_hammer

   • Description: A SMP system modeled after the AMD Opteron. The network can be unordered. The implementation adds an Owner and Exclusive bit to the Directory/Memory controller to avoid Opteron's duplicate data response.

4. MSI_MOSI_CMP_directory

   • Decription: A two-level directory protocol for Chip-Multiprocessors. The L1 and L2 controllers are split, and the L2 cache is shared by all processors on the same chip. Inclusion is maintained between L2s and the L1s, and a sharers list is kept in each L2 cache line.

   Notes:

   • PROCS_PER_CHIP controls the number of CMPs
   • PT_TO_PT and FILE_SPECIFIED are the recommended network topologies for the CMP protocols.
5. MOESI_CMP_directory

   • Description: A two-level directory protocol for Chip-Multiprocessors. Non-inclusive L1/L2 caching with blocking caches. Typically exhibits higher performance than MSI_MOSI_CMP_directory however is more complex and may still have rare protocol bugs

6. MOESI_CMP_token

   • Description: A CMP system based on Token Coherence (TokenCMP).

7. MOSI_SMP_bcast_1level and MOSI_SMP_directory_1level

   • Description: Similar to MOSI_SMP_bcast and MOSI_SMP_directory except that each processor has a single unified cache

8. MESI_SCMP_tiledL2bankDirectory

   • Description: A Single-CMP protocol using L2 caches as directories. Home L2 bank is interleaved by block address. L2 is nominally shared amongst all processors.

     Notes:

     • Must use FILE_SPECIFIED network with TILED g_CACHE_DESIGN.