Overview

The GEMS memory controller allows the timing of DRAM reads and writes to be modeled, so that the performance effects of memory traffic and memory bandwidth may be seen. By convention, protocols that end in "_m" use the memory controller.

This model assumes a DDR2/DDR3 memory running in closed page mode with posted CAS. It models bank busy time, memory bus occupancy and turnaround delays, and refresh. There is currently no support for open page mode or for FB-DIMM.

Each instance of the memory controller models one address bus, one data bus, and any number of DIMMs. Each DIMM has a configurable number of ranks of DRAM. The configuration and delay values are parameterized; please refer to the comments in the rubyconfig.defaults file. The relevant portion is reproduced here: Memory Controller Params

Memory_Controller (last edited 2008-03-08 17:35:59 by LukeYen)