Program Slicing of Hardware Description Languages
E.M. Clarke, M. Fujita, S.P.Rajan, T. Reps, S. Shankar, and T. Teitelbaum
Hardware description languages (HDLs) are used today to describe
circuits at all levels. In large HDL programs, there is a need for
source code reduction techniques to address a myriad of problems in
formal verification, design, simulation, and testing. Program slicing
is a static program analysis technique that allows an analyst to
automatically extract portions of programs relevant to the aspects
being analyzed. We extend program slicing to HDLs, thus allowing for
automatic program reduction to allow the user to focus on relevant
code portions. We have implemented a VHDL slicing tool composed of a
general inter-procedural slicer and a front-end that captures VHDL
execution semantics. This paper provides an overview of program
slicing, a discussion of how to slice VHDL programs, a description of
the resulting tool, and a brief overview of some applications and
experimental results.
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