During a sabbatical visit to Google's Mobile Silicon Team, we reflected on how to make the mobile system on a chip (SoC) selection and design more scientific. Here we contribute a modest step forward with the Gables model. Gables extends Roofline and bottleneck analysis to frame early thinking (e.g., before cycle-level simulation or hardware measure are practical). It seeks to provide the first answers, not the final answers.
This page points to the paper, talks, interactive Gables tools, and open-source Gables Android app.
Gables helped inspire the concept of accelerator-level parallelism that is currently found in Mobile SoCs, and we hypothesize will spread to future computer systems more generally.
Accelerator-level Parallelism
Mark D. Hill and Vijay Janapa Reddi,
Most-recent Talk Slides (6/2020):
PPTX and
PDF
Technion Talk 41-Minute Video (6/2020):
Youtube or
Panoptotech
First Talk Slides (3/2019): PPTX &
PDF
CACM Viewpoint (12/2021): Accelerator-Level Parallelism
SIGARCH Blog (9/2019): Accelerator-Level Parallelism (ALP)
ArXiv (8/2020): html/pdf
Supplementary Material: Gables Home Page
Gables's scaled roofline plots were conceived by Penporn Koanantakool of Google and implemented in the paper, talks, and for this interactive tool by Nikhita Kunati of Wisconsin.
![]() Mark D. Hill starting |
![]() Vijay Janapa Reddi with smartphone |