Dear Colleague:


We are pleased to announce the release of a new issue of Journal of Computing Science and Engineering (JCSE), published by the Korean Institute of Information Scientists and Engineers (KIISE). KIISE is the largest organization for computer scientists in Korea with over 4,000 active members.


Journal of Computing Science and Engineering (JCSE) is a peer-reviewed quarterly journal that publishes high-quality papers on all aspects of computing science and engineering. JCSE aims to foster communication between academia and industry within the rapidly evolving field of Computing Science and Engineering. The journal is intended to promote problem-oriented research that fuses academic and industrial expertise. The journal focuses on emerging computer and information technologies including, but not limited to, embedded computing, ubiquitous computing, convergence computing, green computing, smart and intelligent computing, and human computing. JCSE publishes original research contributions, surveys, and experimental studies with scientific advances.


Please take a look at our new issue posted at All the papers can be downloaded from the Web page.


The contents of the latest issue of Journal of Computing Science and Engineering (JCSE)

Official Publication of the Korean Institute of Information Scientists and Engineers

Volume 14, Number 4, December 2020


pISSN: 1976-4677

eISSN: 2093-8020


* JCSE web page:

* e-submission:


Editor in Chief: Insup Lee (University of Pennsylvania)

Il-Yeol Song (Drexel University)

Jong C. Park (KAIST)

Taewhan Kim (Seoul National University)



JCSE, vol. 14, no. 4, December 2020


[Paper One]

- Title: Reducing CPU-GPU Interferences to Improve CPU performance in Heterogeneous Architectures

- Authors: Hao Wen and Wei Zhang

- Keyword: Heterogeneous architectures, Last Level Cache, Inter-Application Interferences


- Abstract

Current heterogeneous CPU-GPU architectures integrate general-purpose CPUs and highly thread-level parallelized GPUs (graphic processing units) in the same die. The contention in shared resources between CPU and GPU, such as the last level cache (LLC), interconnection network, and DRAM, may degrade both CPU and GPU performance. Our experimental results show that GPU applications tend to have much more power than CPU applications to compete for the shared resources in the LLC and on-chip network, and therefore make CPU suffer from more performance loss. To reduce the GPU's negative impact on CPU performance, we propose a simple yet effective method based on probability to control the LLC replacement policy for reducing the CPU's inter-core conflict misses caused by GPU without significantly impacting GPU performance. In addition, we develop two strategies to combine the probability-based method for the LLC and an existing technique called virtual channel partition (VCP) for the interconnection network to further improve the CPU performance. The first strategy statically uses an empirically pre-determined probability value associated with VCP, which can improve the CPU performance by 26% on average, but degrades GPU performance by 5%. The second strategy uses a sampling method to monitor the network congestion and dynamically adjust the probability value used, which can improve the CPU performance by 24%, and only have 1% or 2% performance overhead on GPU applications.

To obtain a copy of the entire article, click on the link below.
JCSE, vol. 14, no. 4, pp.131-145


[Paper Two]

- Title: VLSI Implementation of Algorithm for Performance Improvement of Minutiae based Fingerprint Recognition System

- Authors: Seungmin Jung

- Keyword: Fingerprint algorithm, Gabor filter, Thinning, VLSI, Minutiae, Verilog-HDL


- Abstract

The fingerprint recognition system has a scheme in which the fingerprint sensor and the algorithm are separated. It is ineffective to operate a total fingerprint algorithm with various simple iterations using only the software environment. This paper proposes an effective fingerprint identification system with VLSI (very large scale integration) hardware architecture for Gabor filter and thinning processing. These two steps occupy the largest portion of CPU processing time in minutiae based fingerprint recognition algorithms. In this paper, we analyze the step-by-step operation of the algorithm using an ARM emulator. We implemented a VLSI logic circuit for hardware processing of Gabor filters and thinning in RTL. The logic is also synthesized and the layout is performed based on automatic placement-routing and postsimulation is performed in the 250n 6-metal CMOS process. The result is compared with the data of a conventional study. The proposed circuit is verified to reduce the algorithm processing time by 73%.

To obtain a copy of the entire article, click on the link below.
JCSE, vol. 14, no. 4, pp.146-153


[Paper Three]

- Title: Semantic Vector Learning using Pretrained Transformers in Natural Language Understanding

- Authors: Sangkeun Jung

- Keyword: Semantic Vector; Semantic Vector Learning; Natural Language Understanding; Transformer


- Abstract

Natural language understanding (NLU) is a core technology for implementing natural interfaces. To implement and support robust NLU, previous studies introduced a neural network approach to learn semantic vector representation by employing the correspondence between text and semantic frame texts as extracted semantic knowledge. In their work, long short-term memory (LSTM)-based text and readers were used to encode both text and semantic frames. However, there exists significant room for performance improvement using recent pretrained transformer encoders. In the present work, as a key contribution, we have extended Jung's framework to work with pretrained transformers for both text and semantic frame readers. In particular, a novel semantic frame processing method is proposed to directly feed the structural form of the semantic frame to transformers. We conducted massive experiments by combining various types of LSTM- or transformer-based text and semantic frame readers on the ATIS, SNIPS, Sim-M, Sim-R, and Weather datasets to find the best suitable configurations for learning effective semantic vector representations. Through the experiments, we concluded that the transformer-based text and semantic frame reader show a stable and rapid learning curve as well as the best performance in similarity-based intent classification and semantic search tasks.

To obtain a copy of the entire article, click on the link below.
JCSE, vol. 14, no. 4, pp.154-162


[Paper Four]

- Title: A Systematic Literature Review on Graphical Password Schemes

- Authors: Tahmina Islam Shammee, Taslima Akter, Muthmainna Mou, Farida Chowdhury, and Md Sadek Ferdous

- Keyword: Graphical Password, authentication, recognition scheme, recall schemes, cued-recall scheme, hybrid scheme, security


- Abstract

Graphical passwords are an alternative to traditional alphanumeric passwords and can similarly be used to secure online accounts. The widely used alphanumeric passwords have memorability issues and users often find it difficult to memorize a large number of unique passwords. Since 1996, researchers have implemented different graphical password schemes (GPSs) to address such security and usability issues. There are a wide variety of such schemes available. To initiate a study in this domain, it is necessary for a researcher to have a good understanding of the existing research. There are a number of existing review articles, but no systematic literature review (SLR). Additionally, the existing reviews have not covered recent papers. This paper aims to fill in these gaps by reviewing existing GPSs, and intends to address their contributions, limitations, the contexts in which they are used, and the relevant algorithms/techniques. To this end, we conducted an SLR of empirical studies on a number of GPSs published from 1996 to 2019. This article also identifies the security threats that the reviewed schemes are resilient against. A number of schemes have been found to have greater resiliency against different attacks, but not a single scheme is completely resistant to all known attacks.

To obtain a copy of the entire article, click on the link below.
JCSE, vol. 14, no. 4, pp.163-185



[Call For Papers]

Journal of Computing Science and Engineering (JCSE), published by the Korean Institute of Information Scientists and Engineers (KIISE) is devoted to the timely dissemination of novel results and discussions on all aspects of computing science and engineering, divided into Foundations, Software & Applications, and Systems & Architecture. Papers are solicited in all areas of computing science and engineering. See JCSE home page at for the subareas.

The journal publishes regularly submitted papers, invited papers, selected best papers from reputable conferences and workshops, and thematic issues that address hot research topics. Potential authors are invited to submit their manuscripts electronically, prepared in PDF files, through, where ScholarOne is used for on-line submission and review. Authors are especially encouraged to submit papers of around 10 but not more than 30 double-spaced pages in twelve point type. The corresponding author's full postal and e-mail addresses, telephone and FAX numbers as well as current affiliation information must be given on the manuscript. Further inquiries are welcome at JCSE Editorial Office, (phone: +82-2-588-9240; FAX: +82-2-521-1352).