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Dark Silicon and the End of Multicore Scaling

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Hadi Esmaeilzadeh, Emily Blem, Renee St. Amant, Karthikeyan Sankaralingam, and Doug Burger. Dark Silicon and the End of Multicore Scaling. In Proceedings of the 38th International Symposium on Computer Architecture, June 2011.

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Abstract

Recently, chip designers have relied on increasing core counts inprocessors to take advantage of the increased transistor countspredicted by Moore's law. However, the reduced rate of voltage scaling, coupled with reducedtransistor capacitance scaling, poses a severe power challenge forcontinued multicore scaling.This paper describes a quantitative study that projects multicorepower and performance for the next five technology generations. Itcombines device scaling, single-core scaling, and multicore scalingusing a novel methodology to provide definitive answers about thespeedup potential of multicore scaling for a set of parallelworkloads.To understand the impact of device scaling on designs, we use ITRS projections, as well as a set of more realisticdevice scaling parameters. To model single-core scaling, we combinemeasurements from over 150 processors to derive Pareto-optimalfrontiers to illustrate area/performance and power/performancesingle-core design tradeoffs. Finally, to model multicore scaling, webuild a detailed performance model that can evaluate upper-boundperformance and lower-bound power for single-thread per core CPU-like andmassively threaded GPU-like multicore chip organizations withsymmetric, asymmetric, dynamic, and fused topologies.Our results show that regardless of chip organization and topology,multicore scaling will be fundamentally limited by power constraints.Even at 22 nm (just two years from now), 25% of the chip must bepowered off, and at 8 nm, this number grows to more than 70%.Through 2024, only 7.9X average speedup is possible acrosscommonly accepted highly parallel workloads, leaving a24X gap from the anticipated performance doubling pergeneration.

BibTeX

 @inproceedings{isca11:darksilicon,
   author={Hadi Esmaeilzadeh and  Emily Blem and Renee St. Amant and Karthikeyan Sankaralingam and Doug Burger},
   title={{Dark Silicon and the End of Multicore Scaling}},
   booktitle="{Proceedings of the 38th International Symposium on Computer Architecture}",
   year={2011},
   abstract = {
 Recently, chip designers have relied on increasing core counts in
 processors to take advantage of the increased transistor counts
 predicted by Moore's law.
 However, the reduced rate of voltage scaling, coupled with reduced
 transistor capacitance scaling, poses a severe power challenge for
 continued multicore scaling.
 This paper describes a quantitative study that projects multicore
 power and performance for the next five technology generations.  It
 combines device scaling, single-core scaling, and multicore scaling
 using a novel methodology to provide definitive answers about the
 speedup potential of multicore scaling for a set of parallel
 workloads.
 To understand the impact of device scaling on
 designs, we use ITRS projections, as well as a set of more realistic
 device scaling parameters.  To model single-core scaling, we combine
 measurements from over 150 processors to derive Pareto-optimal
 frontiers to illustrate area/performance and power/performance
 single-core design tradeoffs. Finally, to model multicore scaling, we
 build a detailed performance model that can evaluate upper-bound
 performance and lower-bound power for single-thread per core CPU-like and
 massively threaded GPU-like multicore chip organizations with
 symmetric, asymmetric, dynamic, and fused topologies.
 Our results show that regardless of chip organization and topology,
 multicore scaling will be fundamentally limited by power constraints.
 Even at 22~nm (just two years from now), 25\% of the chip must be
 powered off, and at 8~nm, this number grows to more than 70\%.
 Through 2024, only 7.9X average speedup is possible across
 commonly accepted highly parallel workloads, leaving a
 24X gap from the anticipated performance doubling per
 generation.
 },
   bib_dl_pdf = {http://bit.ly/fmPjY4},
   bib_pubtype = {Refereed Conference,Micro Top Picks},
   bib_rescat = {Architecture},
   MONTH = {June}
 }

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