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A Unified Model for Timing Speculation: Evaluating the Impact of Technology Scaling, CMOS Design Style, and Fault Recovery Mechanism

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Marc de Kruijf, Shuou Nomura, and Karthikeyan Sankaralingam. A Unified Model for Timing Speculation: Evaluating the Impact of Technology Scaling, CMOS Design Style, and Fault Recovery Mechanism. In Proceedings of the 40th International Conference on Dependable Systems and Networks, 2010.

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Abstract

Due to fundamental device properties, energy efficiencyfrom CMOS scaling is showing diminishing improvements.To overcome the energy efficiency challenges, timing speculationhas been proposed to optimize for common-case timingconditions, with errors occurring under worst-case conditionsdetected and corrected in hardware. Although varioustiming speculation techniques have been proposed, nogeneral framework exists for reasoning about the trade-offsand high-level design considerations of timing speculation.This paper develops two models to study the end-to-endbehavior of timing speculation: a hardware-level efficiencymodel that considers the effects of process variations onpath delays, and a complementary system-level recoverymodel. When combined, the models are used to assess theimpact of technology scaling, CMOS design style, and faultrecovery mechanism on the efficiency of timing speculation.Our results show that (1) efficiency gains from timingspeculation do not improve as technology scales, (2) ultralowpower (sub-threshold) CMOS designs benefit most fromtiming speculation we report a 47% potential energydelayreduction, and (3) fine-grained fault recovery is keyto significant energy improvements. The combined modeluses only high-level inputs to derive quantitative energy efficiencybenefits without any need for detailed simulation,making it a potentially useful tool for hardware developers.

BibTeX

 @inproceedings{dsn10:timing,
   author={Marc de Kruijf and Shuou Nomura and Karthikeyan Sankaralingam},
   title={A Unified Model for Timing Speculation: Evaluating the Impact of Technology Scaling, CMOS Design Style, and Fault Recovery Mechanism},
   booktitle="{Proceedings of the 40th International Conference on Dependable Systems and Networks}",
   year={2010},
   abstract = {
 Due to fundamental device properties, energy efficiency
 from CMOS scaling is showing diminishing improvements.
 To overcome the energy efficiency challenges, timing speculation
 has been proposed to optimize for common-case timing
 conditions, with errors occurring under worst-case conditions
 detected and corrected in hardware. Although various
 timing speculation techniques have been proposed, no
 general framework exists for reasoning about the trade-offs
 and high-level design considerations of timing speculation.
 This paper develops two models to study the end-to-end
 behavior of timing speculation: a hardware-level efficiency
 model that considers the effects of process variations on
 path delays, and a complementary system-level recovery
 model. When combined, the models are used to assess the
 impact of technology scaling, CMOS design style, and fault
 recovery mechanism on the efficiency of timing speculation.
 Our results show that (1) efficiency gains from timing
 speculation do not improve as technology scales, (2) ultralow
 power (sub-threshold) CMOS designs benefit most from
 timing speculation  we report a 47\% potential energydelay
 reduction, and (3) fine-grained fault recovery is key
 to significant energy improvements. The combined model
 uses only high-level inputs to derive quantitative energy efficiency
 benefits without any need for detailed simulation,
 making it a potentially useful tool for hardware developers.
 },
   bib_dl_pdf = {http://www.cs.wisc.edu/vertical/papers/2010/dsn10-timing.pdf},
   bib_dl_ppt = {http://www.cs.wisc.edu/vertical/talks/2010/dsn10-timing.pptx},
   bib_pubtype = {Refereed Conference},
   bib_rescat = {Architecture}
 }

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