internal:dyser-internal-tutorial
Differences
This shows you the differences between two versions of the page.
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internal:dyser-internal-tutorial [2013/06/07 10:46] chenhan [Hand DySERized Benchmark] |
internal:dyser-internal-tutorial [2013/06/07 14:15] (current) chenhan [Hand DySERized Benchmark] |
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| {{:internal:fu-created.png?200|}} | {{:internal:fu-created.png?200|}} | ||
| - | Double click on the FU, wou will find the cursor becomes a triangle which has same color as the FU. | + | Double click on the FU, you will find the cursor becomes a triangle which has the same color as the FU. |
| Now you can click on the edges to create datapath. Next, you can create primary input (PI) and primary output (PO) on the switches.\\ | Now you can click on the edges to create datapath. Next, you can create primary input (PI) and primary output (PO) on the switches.\\ | ||
| {{:internal:sw-menu.png|}} | {{:internal:sw-menu.png|}} | ||
| - | The input and output can be at any switch, each switch can have two inputs and two output. (This logical view of DySER is different from the hardware implementation.) You can click on ''Show Port Numbers'' to find out what is the port number in the configuration. **The port number is important and we will change it later** | + | The input and output can be at any switch, and each switch can have two inputs and two outputs. (This logical view of DySER is different from the hardware implementation.) You can click on ''Show Port Numbers'' to find out what is the port number of the PIs/POs in the configuration. **The port number is important and we will use it later** |
| Use ''file->save config'' to save the config file to disk. We will use this file to generate a DySER core verilog RTL. | Use ''file->save config'' to save the config file to disk. We will use this file to generate a DySER core verilog RTL. | ||
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| * ''DyLOADPD(mem, port)'' broadcast load, loads to a special vector port. | * ''DyLOADPD(mem, port)'' broadcast load, loads to a special vector port. | ||
| - | Before modifying the code, use genCore.py to generate the verilog RTL. This is important because the logical view is different than the actual RTL, and we need to have a port mapping to map the logical ports to the actual ports in RTL. | + | Before modifying the code, use genCore.py to generate the RTL verilog. Because the logical view is different than the actual RTL, we need to have a port mapping to map the logical ports to the actual physical ports in RTL. |
| Use ''hardDySER/tools/genCore.py'' to read the created config file. | Use ''hardDySER/tools/genCore.py'' to read the created config file. | ||
| + | <code> | ||
| + | python genCore.py -f <config_file> | ||
| + | </code> | ||
| + | A ''<config_file>.hardDYSER.conf'' will be created at the same directory. In this file, you can find the splyser port mapping. Follow this port mapping to add DySER sends and receives to the code. Now you can compile and simulate in GEM5 and VCS. You can refer to the benchmarks in ''hardDYSER/'' to see the config files (''*.hardDySER'') and to see how to use the macros in c. | ||
| + | [TODO: tutorial of genRom and broadcast load] | ||
internal/dyser-internal-tutorial.1370619978.txt.gz ยท Last modified: 2013/06/07 10:46 by chenhan
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