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--- internal:dyser-internal-tutorial [2013/06/06 22:07]
chenhan [Hand DySERized Benchmark]
+++ internal:dyser-internal-tutorial [2013/06/07 14:15] (current)
chenhan [Hand DySERized Benchmark]
@@ Line 99: / Line 99: @@
 ==== Hand DySERized Benchmark ====
-The first step is to find out the computation in the program and create a DySER schedule. execute the software tool ''dytools/dysched'' you will see:
+The first step is to read the code, find out the computation in the program and then create a DySER schedule.
-{{:internal:dysched.png?200|}}
+Execute the software tool ''dytools/dysched'' you will see:\\
+{{:internal:dysched.png|250}}
+[TODO: detailed tutorial of dysched]
+Right click on FU to assign functions to the functional unit:\\
+{{:internal:fu-menu.png|}}
+After you assign the function, FU will be colored and an edge will be created.\\
+{{:internal:fu-created.png?200|}}
+Double click on the FU, you will find the cursor becomes a triangle which has the same color as the FU.
+Now you can click on the edges to create datapath. Next, you can create primary input (PI) and primary output (PO) on the switches.\\
+{{:internal:sw-menu.png|}}
+The input and output can be at any switch, and each switch can have two inputs and two outputs. (This logical view of DySER is different from the hardware implementation.) You can click on ''Show Port Numbers'' to find out what is the port number of the PIs/POs in the configuration. **The port number is important and we will use it later**
+Use ''file->save config'' to save the config file to disk. We will use this file to generate a DySER core verilog RTL.
+Several limitations are:
+  * The ''genCore'' script can only generate DySER core with 2-fanout switches. A 3-fanout (or more) switch will have collide signals in RTL.
+  * We only have 32 input and 32 output in the OpenSPARC-DySER interface.
+  * Only a subset of functional units are supported.
+The saved configuration file has the dimension and a number of switch and FU declaration.
+With the port number in mind, we can modify the c code with the macros in ''opensparc/verif/diag/c/include/dyser-dlp-sparc.h'':
+  * ''DySEND(var, port)'' send data from register to DySER.
+  * ''DyRECV(port, var)'' receive data from DySER to register.
+  * ''DyLOAD(mem, port)'' load data from memory to DySER.
+  * ''DySTORE(port, mem)'' store data from DySER to memory.
+  * ''DyLOADPD(mem, port)'' broadcast load, loads to a special vector port.
+Before modifying the code, use genCore.py to generate the RTL verilog. Because the logical view is different than the actual RTL, we need to have a port mapping to map the logical ports to the actual physical ports in RTL.
+Use ''hardDySER/tools/genCore.py'' to read the created config file.
+<code>
+python genCore.py -f <config_file>
+</code>
+A ''<config_file>.hardDYSER.conf'' will be created at the same directory. In this file, you can find the splyser port mapping. Follow this port mapping to add DySER sends and receives to the code. Now you can compile and simulate in GEM5 and VCS. You can refer to the benchmarks in ''hardDYSER/'' to see the config files (''*.hardDySER'') and to see how to use the macros in c.
+[TODO: tutorial of genRom and broadcast load]

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