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[Knight, 1986]
 
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Thomas F. Knight (Aug 1986).
An Architecture for Mostly Functional Languages.
In: Proceedings of ACM Lisp and Functional Programming Conference. pp. 500--519.
[Adve, 1990]
 
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Sarita V.and Hill Adve (May 1990).
Weak Ordering - A New Definition.
In: Proceedings of the 17th Annual International Symposium on Computer Architecture. pp. 2--14.
[Gharachorloo et al., 1990]
 
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Kourosh Gharachorloo and Daniel Lenoski and James Laudon and Philip Gibbons and Anoop Gupta and John Hennessy (May 1990).
Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors.
In: Proceedings of the 17th Annual International Symposium on Computer Architecture. pp. 15--26.
[Adve et al., 1991]
 
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Sarita V. Adve and Mark D. Hill and Barton P. Miller and Robert H. B. Netzer (May 1991).
Detecting Data Races on Weak Memory Systems.
In: Proceedings of the 18th Annual International Symposium on Computer Architecture. pp. 234--243.
[Adve and Gharachorloo, 1996]
 
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Sarita V. Adve and Kourosh Gharachorloo (Dec 1996).
Shared Memory Consistency Models: A Tutorial.
In: IEEE Computer, 29(12):66--76.
[Plakal et al., 1998]
 
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Manoj Plakal and Daniel J. Sorin and Anne E. Condon and Mark D. Hill (Jun 1998).
Lamport Clocks: Verifying a Directory Cache-Coherence Protocol.
In: Proceedings of the Tenth ACM Symposium on Parallel Algorithms and Architectures. pp. 67--76.
[Hill, 1998]
 
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Mark D. Hill (Aug 1998).
Multiprocessors Should Support Simple Memory Consistency Models.
In: IEEE Computer, 31(8):28--34.
[Gniady et al., 1999]
 
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Chris Gniady and Babak Falsafi and T. N. Vijaykumar (May 1999).
Is SC + ILP = RC?
In: International Symposium on Computer Architecture. pp. 162--171.
[Rajwar and Goodman, 2001]
 
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Ravi Rajwar and James R. Goodman (Dec 2001).
Speculative Lock Elision: Enabling Highly Concurrent Multithreaded Execution.
In: Proceedings of the 34th International Symposium on Microarchitecture. pp. 294--305.
[Sorin et al., 2002]
 
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Daniel J. Sorin and Milo M. K. Martin and Mark D. Hill and David A. Wood (May 2002).
SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery.
In: Proceedings of the 29th Annual International Symposium on Computer Architecture. pp. 123--134.
[Gniady and Falsafi, 2002]
 
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Chris Gniady and Babak Falsafi (Sep 2002).
Speculative Sequential Consistency with Little Custom Storage.
In: International Conference on Parallel Architectures and Compilation Techniques. pp. 179--188.
[Martinez and Torrellas, 2002]
 
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Jose F. Martinez and Josep Torrellas (Oct 2002).
Speculative Synchronization: Applying Thread-Level Speculation to Explicitly Parallel Applications.
In: Proceedings of the Tenth Symposium on Architectural Support for Programming Languages and Operating Systems. pp. 18--29.
[Xu et al., 2003]
 
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Min Xu and Rastislav Bodik and Mark D. Hill (Jun 2003).
A ``Flight Data Recorder'' for Enabling Full-System Multiprocessor Deterministic Replays.
In: Proceedings of the 30th Annual International Symposium on Computer Architecture. pp. 122--133.
[Gniady and Falsafi, 2003]
 
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Chris Gniady and Babak Falsafi ( 2003).
Speculative Sequential Consistency with Little Custom Storage.
In: Journal of Instruction-Level Parallelism, 5.
[Kozyrakis and Olukotun, 2005]
 
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Christos Kozyrakis and Kunle Olukotun (Feb 2005).
ATLAS: A Scalable Emulator for Transactional Parallel System.
In: Workshop on Architecture Research using FPGA Platforms, 11th International Symposium on High-Performance Computer Architectur.
[Xu et al., 2005]
 
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Min Xu and Rastislav Bodik and Mark D. Hill (Jun 2005).
A Serializability Violation Detector for Shared-Memory Server Programs.
In: Proceedings of the SIGPLAN 2005 Conference on Programming Language Design and Implementation. pp. 1--14.
[Chafi et al., 2005]
 
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Hassan Chafi and Chi Cao Minh and Austen McDonald and Brian D. Carlstrom and JaeWoong Chung and Lance Hammond and Christos Kozyrakis and Kunle Olukotun (June 2005).
TAPE: A Transactional Application Profiling Environment.
In: ICS '05: Proceedings of the 19th annual international conference on Supercomputing. pp. 199--208.
[Shriram et al., 2005]
 
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Arrvindh Shriram and Virendra J. Marathe and Sandhya Dwarkadas and Michael L. Scott and David Eisenstat and Christopher Heriot and William N. Scherer III and Michael F. Spear (Dec 2005).
Hardware Acceleration of Software Transactional Memory.
Technical Report Nr. TR 887. Computer Science Department, University of Rochester. Revised, March 2006; condensed version submitted for publication.
[Chung et al., 2006]
 
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JaeWoong Chung and Hassan Chafi and Chi Cao Minh and Austen McDonald and Brian D. Carlstrom and Christos Kozyrakis and Kunle Olukotun (Feb 2006).
The Common Case Transactional Behavior of Multithreaded Programs.
In: 12th International Symposium on High Performance Computer Architecture (HPCA).
[Ceze et al., 2006]
 
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Luis Ceze and James Tuck and Calin Cascaval and Josep Torrellas (June 2006).
Bulk Disambiguation of Speculative Threads in Multiprocessors.
In: Proceedings of the 33rd Annual International Symposium on Computer Architecture.
[Shriraman et al., 2006]
 
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Arrvindh Shriraman and Virendra J. Marathe and Sandhya Dwarkadas and Michael L. Scott and David Eisenstat and Christopher Heriot and William N. Scherer III and Michael F. Spear (Jun 2006).
Hardware Acceleration of Software Transactional Memory.
In: ACM SIGPLAN Workshop on Transactional Computing. Held in conjunction with PLDI 2006. Expanded version available as TR 887, Department of Computer Science, University of Rochester, December 2005, revised March 2006.
[Ceze et al., 2007]
 
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Luis Ceze and Pablo Montesinos and Christoph von Praun and Josep Torrellas (Feb 2007).
Colorama: Architectural Support for Data-Centric Synchronization.
In: Proceedings of the 13th International Symposium on High-Performance Computer Architecture.
[Spear et al., 2007]
 
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Michael F. Spear and Arrvindh Shriraman and Hemayet Hossain and Sandhya Dwarkadas and Michael L. Scott (Mar 2007).
Alert-on-Update: A Communication Aid for Shared Memory Multiprocessors (poster paper).
In: Proceedings of the Twelfth ACM Symposium on Principles and Practice of Parallel Programming.
[Neelakantam et al., 2007]
 
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Naveen Neelakantam and Ravi Rajwar and Suresh Srinivas and Uma Srinivasan and Craig Zilles (June 2007).
Hardware Atomicity for Reliable Software Speculation .
In: Proceedings of the 34th Annual International Symposium on Computer Architecture.
[Spear et al., 2007]
 
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Michael F. Spear and Arrvindh Shriraman and Luke Dalessandro and Sandhya Dwarkadas and Michael L. Scott (Jun 2007).
Nonblocking Transactions Without Indirection Using Alert-on-Update.
In: Proceedings of the 19th Annual ACM SYMP on Parallelism in Algorithms and Architectures. San Diego, CA.
[Waliullah and Stenstrom, 2007]
 
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M. M. Waliullah and Per Stenstrom (Aug 2007).
Starvation-Free Transactional Memory System Protocols.
In: Proceedings of the 13th Euro-Par Conference: European Conference on Parallel and Distributed Computing. pp. 280--291.
[Rossbach et al., 2007]
 
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Christopher J. Rossbach and Owen S. Hofmann and Donald E. Porter and Hany E. Ramadan and Aditya Bhandari and Emmett Witchel ( 2007).
TxLinux: using and managing hardware transactional memory in an operating system.
In: SOSP '07: Proceedings of twenty-first ACM SIGOPS Symposium on Operating Systems Principles. New York, NY, USA, pp. 87--102. Published by ACM.
[Wee et al., 2007]
 
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Sewook Wee and Jared Casper and Njuguna Njoroge and Yuriy Teslyar and Daxia Ge and Christos Kozyrakis and Kunle Olukotun ( 2007).
A Practical FPGA-based Framework for Novel CMP Research.
In: FPGA '07: Proceedings of the 2007 ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays. pp. 116--125. ACM Press, New York, NY, USA.
[Tuck et al., 2008]
 
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James Tuck and Wonsun Ahn and Luis Ceze and Josep Torrellas (mar 2008).
SoftSig: software-exposed hardware signatures for code analysis and optimization.
In: ASPLOS~'08: Proc. 13th International Conference on Architectural Support for Programming Languages and Operating Systems. pp. 145--156.
[Waliullah and Stenstrom, 2008]
 
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MM Waliullah and Per Stenstrom (April 2008).
Intermediate Checkpointing with Conflicting Access Prediction in Transactional Memory Systems.
In: Proceedings of the 22nd IEEE International Parallel and Distributed Processing Symposium.
[Lucia et al., 2008]
 
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Brandon Lucia and Joseph Devietti and Karin Strauss and Luis Ceze (Jun 2008).
Atom-Aid: Detecting and Surviving Atomicity Violations.
In: ISCA~'08: Proc. 35th Annual International Symposium on Computer Architecture. pp. 277--288.
[Chung et al., 2008]
 
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JaeWoong Chung and Woongki Baek and Nathan Grasso Bronson and Jiwon Seo and Christos Kozyrakis and Kunle Olukotun (jun 2008).
ASeD: Availability, Security, and Debugging Support using Transactional Memory (poster).
In: SPAA~'08: Proc. 20th Symposium on Parallelism in Algorithms and Architectures. pp. 366--366.
[Kumar et al., 2008]
 
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Sanjeev Kumar and Daehyun Kim and Mikhail Smelyanskiy and Yen-Kuang Chen and Jatin Chhugani and Christopher J. Hughes and Changkyu Kim and Victor W. Lee and Anthony D. Nguyen (Jun 2008).
Atomic Vector Operations on Chip Multiprocessors.
In: Proceedings of the 35th Annual International Symposium on Computer Architecture. pp. 441--452. Published by ACM.
[Shriraman et al., 2008]
 
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Arrvindh Shriraman and Sandhya Dwarkadas and Michael L. Scott (Jun 2008).
Flexible Decoupled Transactional Memory Support.
In: Proceedings of the 35th Annual International Symposium on Computer Architecture.
[Rui et al., 2008]
 
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Guo Rui and Hong An and Ruiling Dou and Ming Cong and Yaobin Wang and Qi Li (Aug 2008).
LogSPoTM: A Scalable Thread Level Speculation Model Based on Transactional Memory.
In: Proc. 13th Asia-Pacific Computer Systems Architecture Conference.
[Poe et al., 2008]
 
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James Poe and Chang-Burm Cho and Tao Li ( 2008).
Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design.
In: SBAC-PAD '08: Proceedings of the 2008 20th International Symposium on Computer Architecture and High Performance Computing. Washington, DC, USA, pp. 159--166. Published by IEEE Computer Society.
[Chung et al., 2009]
 
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JaeWoong Chung and Woongki Baek and Christos Kozyrakis (jun 2009).
Fast memory snapshot for concurrent programming without synchronization.
In: ICS~'09: Proc. 23rd international conference on Supercomputing. pp. 117--125.
[Xekalakis et al., 2009]
 
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Polychronis Xekalakis and Nikolas Ioannou and Marcelo Cintra (jun 2009).
Combining thread level speculation helper threads and runahead execution.
In: ICS~'09: Proc. 23rd international conference on Supercomputing. pp. 410--420.
[Hossain et al., 2009]
 
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Hemayet Hossain and Sandhya Dwarkadas and Michael C. Huang (sep 2009).
DDCache: Decoupled and Delegable Cache Data and Metadata.
In: PACT~'09: Proc. 18th International Conference on Parallel Architectures and Compilation Techniques.
[Quislant et al., 2009]
 
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Ricardo Quislant and Eladio Gutierrez and Oscar. Plata (sep 2009).
Improving Signatures by Locality Exploitation for Transactional Memory.
In: PACT~'09: Proc. 18th International Conference on Parallel Architectures and Compilation Techniques.
[Ahn et al., 2009]
 
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Wonsun Ahn and Shanxiang Qi and Jae-Woo Lee and Marios Nicolaides and Xing Fang and Josep Torrellas and David Wong and Samuel Midkiff (Dec 2009).
BulkCompiler: High-Performance Sequential Consistency through Cooperative Compiler and Hardware Support.
In: Proceedings of the 42nd International Symposium on Microarchitecture.
[Chaudhry et al., 2009]
 
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Shailender Chaudhry and Robert Cypher and Magnus Ekman and Martin Karlsson and Anders Landin and Sherman Yip and H\rakan Zeffer and Marc Tremblay ( 2009).
Rock: A High-Performance Sparc CMT Processor.
In: IEEE Micro, 29(2):6-16.
[Blake et al., 2009]
 
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Geoffrey Blake and Ronald G. Dreslinski and Trevor Mudge ( 2009).
Proactive transaction scheduling for contention management.
In: Micro-42: Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture. New York, NY, USA, pp. 156--167. Published by ACM.
[Blundell et al., 2009]
 
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Colin Blundell and Milo M.K. Martin and Thomas F. Wenisch ( 2009).
InvisiFence: performance-transparent memory ordering in conventional multiprocessors.
In: ISCA~'09: Proc. 36th annual International Symposium on Computer Architecture. pp. 233--244.
[Chaudhry et al., 2009]
 
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Shailender Chaudhry and Robert Cypher and Magnus Ekman and Martin Karlsson and Anders Landin and Sherman Yip and H\aakan Zeffer and Marc Tremblay ( 2009).
Simultaneous speculative threading: a novel pipeline architecture implemented in sun's rock processor.
In: ISCA~'09: Proc. 36th annual International Symposium on Computer Architecture. pp. 484--495.
[Poe et al., 2009]
 
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James Poe and Clay Hughes and Tao Li ( 2009).
TransMetric: architecture independent workload characterization for transactional memory benchmarks.
In: ICS '09: Proceedings of the 23rd international conference on Supercomputing. New York, NY, USA, pp. 491--492. Published by ACM.