usermode/library/common/spinlock.h

#ifndef _ASM_X86_SPINLOCK_H
#define _ASM_X86_SPINLOCK_H

/*
 * Your basic SMP spinlocks, allowing only a single CPU anywhere
 *
 * Simple spin lock operations.  There are two variants, one clears IRQ's
 * on the local processor, one does not.
 *
 * These are fair FIFO ticket locks, which are currently limited to 256
 * CPUs.
 *
 * (the type definitions are in asm/spinlock_types.h)
 */

typedef struct arch_spinlock {
        unsigned int slock;
} arch_spinlock_t;

# define LOCK_PTR_REG "D"
# define REG_PTR_MODE "q"


/*
 * Ticket locks are conceptually two parts, one indicating the current head of
 * the queue, and the other indicating the current tail. The lock is acquired
 * by atomically noting the tail and incrementing it by one (thus adding
 * ourself to the queue and noting our position), then waiting until the head
 * becomes equal to the the initial value of the tail.
 *
 * We use an xadd covering *both* parts of the lock, to increment the tail and
 * also load the position of the head, which takes care of memory ordering
 * issues and should be optimal for the uncontended case. Note the tail must be
 * in the high part, because a wide xadd increment of the low part would carry
 * up and contaminate the high part.
 *
 * With fewer than 2^8 possible CPUs, we can use x86's partial registers to
 * save some instructions and make the code more elegant. There really isn't
 * much between them in performance though, especially as locks are out of line.
 */
#define TICKET_SHIFT 8

static __always_inline void __ticket_spin_lock(volatile arch_spinlock_t *lock)
{
        short inc = 0x0100;

        asm volatile (
                "lock; xaddw %w0, %1\n"
                "1:\t"
                "cmpb %h0, %b0\n\t"
                "je 2f\n\t"
                "rep ; nop\n\t"
                "movb %1, %b0\n\t"
                /* don't need lfence here, because loads are in-order */
                "jmp 1b\n"
                "2:"
                : "+Q" (inc), "+m" (lock->slock)
                :
                : "memory", "cc");
}

/*
static __always_inline int __ticket_spin_trylock(arch_spinlock_t *lock)
{
        int tmp, new;

        asm volatile("movzwl %2, %0\n\t"
                     "cmpb %h0,%b0\n\t"
                     "leal 0x100(%" REG_PTR_MODE "0), %1\n\t"
                     "jne 1f\n\t"
                     LOCK_PREFIX "cmpxchgw %w1,%2\n\t"
                     "1:"
                     "sete %b1\n\t"
                     "movzbl %b1,%0\n\t"
                     : "=&a" (tmp), "=&q" (new), "+m" (lock->slock)
                     :
                     : "memory", "cc");

        return tmp;
}
*/

static __always_inline void __ticket_spin_unlock(volatile arch_spinlock_t *lock)
{
        asm volatile("incb %0"
                     : "+m" (lock->slock)
                     :
                     : "memory", "cc");
}

/*
static inline int __ticket_spin_is_locked(arch_spinlock_t *lock)
{
        int tmp = ACCESS_ONCE(lock->slock);

        return !!(((tmp >> TICKET_SHIFT) ^ tmp) & ((1 << TICKET_SHIFT) - 1));
}

static inline int __ticket_spin_is_contended(arch_spinlock_t *lock)
{
        int tmp = ACCESS_ONCE(lock->slock);

        return (((tmp >> TICKET_SHIFT) - tmp) & ((1 << TICKET_SHIFT) - 1)) > 1;
}

*/


#endif /* _ASM_X86_SPINLOCK_H */

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