usermode/library/atomic_ops/ordered_except_wr.h

00001 /*
00002  * Copyright (c) 2003 by Hewlett-Packard Company.  All rights reserved.
00003  *
00004  * Permission is hereby granted, free of charge, to any person obtaining a copy
00005  * of this software and associated documentation files (the "Software"), to deal
00006  * in the Software without restriction, including without limitation the rights
00007  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
00008  * copies of the Software, and to permit persons to whom the Software is
00009  * furnished to do so, subject to the following conditions:
00010  *
00011  * The above copyright notice and this permission notice shall be included in
00012  * all copies or substantial portions of the Software.
00013  *
00014  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
00015  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
00016  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
00017  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
00018  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
00019  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
00020  * SOFTWARE.
00021  */
00022 
00023 /*
00024  * These are common definitions for architectures that provide processor
00025  * ordered memory operations except that a later read may pass an
00026  * earlier write.  Real x86 implementations seem to be in this category,
00027  * except apparently for some IDT WinChips, which we ignore.
00028  */
00029 
00030 #include "read_ordered.h"
00031 
00032 AO_INLINE void
00033 AO_nop_write(void)
00034 {
00035   AO_compiler_barrier();
00036   /* sfence according to Intel docs.  Pentium 3 and up. */
00037   /* Unnecessary for cached accesses?                   */
00038 }
00039 
00040 #define AO_HAVE_NOP_WRITE
00041 
00042 #if defined(AO_HAVE_store)
00043 
00044 AO_INLINE void
00045 AO_store_write(volatile AO_t *addr, AO_t val)
00046 {
00047   AO_compiler_barrier();
00048   AO_store(addr, val);
00049 }
00050 # define AO_HAVE_store_write
00051 
00052 # define AO_store_release(addr, val) AO_store_write(addr, val)
00053 # define AO_HAVE_store_release
00054 
00055 #endif /* AO_HAVE_store */
00056 
00057 #if defined(AO_HAVE_char_store)
00058 
00059 AO_INLINE void
00060 AO_char_store_write(volatile unsigned char *addr, unsigned char val)
00061 {
00062   AO_compiler_barrier();
00063   AO_char_store(addr, val);
00064 }
00065 # define AO_HAVE_char_store_write
00066 
00067 # define AO_char_store_release(addr, val) AO_char_store_write(addr, val)
00068 # define AO_HAVE_char_store_release
00069 
00070 #endif /* AO_HAVE_char_store */
00071 
00072 #if defined(AO_HAVE_short_store)
00073 
00074 AO_INLINE void
00075 AO_short_store_write(volatile unsigned short *addr, unsigned short val)
00076 {
00077   AO_compiler_barrier();
00078   AO_short_store(addr, val);
00079 }
00080 # define AO_HAVE_short_store_write
00081 
00082 # define AO_short_store_release(addr, val) AO_short_store_write(addr, val)
00083 # define AO_HAVE_short_store_release
00084 
00085 #endif /* AO_HAVE_short_store */
00086 
00087 #if defined(AO_HAVE_int_store)
00088 
00089 AO_INLINE void
00090 AO_int_store_write(volatile unsigned int *addr, unsigned int val)
00091 {
00092   AO_compiler_barrier();
00093   AO_int_store(addr, val);
00094 }
00095 # define AO_HAVE_int_store_write
00096 
00097 # define AO_int_store_release(addr, val) AO_int_store_write(addr, val)
00098 # define AO_HAVE_int_store_release
00099 
00100 #endif /* AO_HAVE_int_store */

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