Modern processor architectures achieve high levels of performance through instruction-level parallelism (ILP). However the amount of ILP is limited by dependences imposed by control and data flow in programs. Aggressive hardware implementations of these architectures use prediction and speculation of various kinds to overcome these limitations. However, these prediction schemes are not perfect and the misprediction penalty is high.
Predication has been proposed as a means of eliminating limiting control flow. It also gives the compiler more control over the execution schedule. Hardware support for explicitly speculative code is another method of alleviating control dependences, which can be exploited by compilers. These two schemes are especially relevant since the upcoming IA-64 (Merced) processor architecture announced by Intel & HP includes support for predication and speculative load instructions.
In this talk, I shall describe ways in which optimizing compilers can exploit predication (using hyperblock scheduling) and speculation (using sentinel scheduling) to schedule code aggressively and expose more ILP to the underlying hardware. The talk is based mainly on publications by the members of the IMPACT Compiler group at UIUC and the PL/Compilers group at HP Labs.