%Z -------------------------------------------------------------------------
%Z
%Z	Refer/bib bibliographic entries for the 19th
%Z	INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE
%Z	(1992) created by Julie Fingerson and Mark D. Hill
%Z 
%Z	These entries are correct to the best of our knowledge,
%Z	but we accept no responsibility for the consequences of
%Z	any errors.  Email corrections to hoffman@cs.wisc.edu.
%Z	Last change:  Thu Mar 30 14:32:06 CST 1995
%Z
%Z -------------------------------------------------------------------------
%Z

%T A Performance Study of Memory Consistency Models
%A Richard N. Zucker
%A Jean-Loup Baer
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 2-12
 
%T Lazy Release Consistency for Software Distributed Shared Memory
%A Pete Keleher
%A Alan L. Cox
%A Willy Zwaenepoel
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 13-21

%T Hiding Memory Latency using Dynamic Scheduling in Shared-Memory Multiprocessors
%A Kourosh Gharachorloo
%A Anoop Gupta
%A John Hennessy
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 22-33

%T Effects of Building Blocks on the Peformance of Super-Scalar Architectures
%A Edil S. T. Fernandes
%A Fernando M. B. Barbosa
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 36-45

%T Limits of Control Flow on Parallelism
%A Monica S. Lam
%A Robert P. Wilson
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 46-57

%T The Expandable Split Window Paradigm for Exploiting Fine-Grain Parallelism
%A Manoj Franklin
%A Gurindar S. Sohi
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 58-67

%T Towards a Shared-Memory Massively Parallel Multiprocessor
%A Daniel Litaize
%A Abdelaziz Mzoughi
%A Christine Rochange
%A Pascal Sainrat
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 70-79

%T Comparative Performance Evaluation of Cache-Coherent NUMA and COMA Architectures
%A Per Stenstrom
%A Truman Joe
%A Anoop Gupta
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 80-91

%T The DASH Prototype: Implementation and Performance
%A Daniel Lenoski
%A James Laudon
%A Truman Joe
%A David Nakahira
%A Luis Stevens
%A Anoop Gupta
%A John Hennessy
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 92-103

%T Performance Evaluation of a Decoded Instruction Cache for Variable Instruction-Length Computers
%A Gideon Intrater
%A Ilan Spillinger
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 106-113

%T A Simulation Based Study of TLB Performance
%A J. Bradley Chen
%A Anita Borg
%A Norman P. Jouppi
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 114-123

%T Alternative Implementations of Two-Level Adaptive Branch Prediction
%A Tse-Yu Yeh
%A Yale N. Patt
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 124-134

%T An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads
%A Hiroaki Hirata
%A Kozo Kimura
%A Satoshi Nagamine
%A Yoshiyuki Mochizuki
%A Akio Nishimura
%A Yoshimori Nakase
%A Teiji Nishizawa
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 136-145

%T Thread-based Programming for the EM-4 Hybrid Dataflow Machine
%A Mitsuhisa Sato
%A Yuetsu Kodama
%A Shuichi Sakai
%A Yoshinori Yamaguchi
%A Yasuhito Koumura
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 146-155

%T *T: A Multithreaded Massively Parallel Architecture
%A R. S. Nikhil
%A G. M. Papadopoulos
%A Arvind
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 156-167

%T Adjustable Block Size Coherent Caches
%A Czarek Dubnicki
%A Thomas J. LeBlanc
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 170-180

%T Performance Optimization of Pipelined Primary Caches
%A Kunle Olukotun
%A Trevor Mudge
%A Richard Brown
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 181-190

%T Cache Replacement with Dynamic Exclusion
%A Scott McFarling
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 191-200

%T Processor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism
%A Stephen W. Keckler
%A William J. Dally
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 202-213

%T Improved Multithreading Techniques for Hiding Communication Latency in Multiprocessors
%A Bob Boothe
%A Abhiram Ranade
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 214-223

%T Instruction-level Parallelism in Prolog: Analysis and Architectural Support
%A Alessandro De Gloria
%A Paolo Faraboschi
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 224-233

%T Memory Latency Effects in Decoupled Architectures With a Single Data Memory Module
%A Lizyamma Kurian
%A Paul T. Hulina
%A Lee D. Coraor
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 236-245

%T Interleaved Parallel Schemes: Improving Memory Throughput on Supercomputers
%A Andre Seznec
%A Jacques Lenfant
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 246-255

%T Active Messages: A Mechanism for Integrated Communication and Computation
%A Thorsten von Eicken
%A David E. Culler
%A Seth Copen Goldstein
%A Klaus Erik Schauser
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 256-266

%T Planar-Adaptive Routing: Low-cost Adaptive Networks for Multiprocessors
%A Andrew A. Chien
%A Jae H. Kim
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 268-277

%T The Turn Model for Adaptive Routing
%A Christopher J. Glass
%A Lionel M. Ni
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 278-287

%T Low-Latency Message Communication Support for the AP1000
%A Toshiyuki Shimizu
%A Takeshi Horie
%A Hiroaki Ishihata
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 288-297

%T Futurebus+ as an I/O Bus: Profile B
%A Barbara P. Aichinger
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 300-307

%T A Study of I/O System Organizations 
%A A. L. Narasimha Reddy
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 308-317

%T Comparison of Sparing Alternatives for Disk Arrays
%A Jai Menon
%A Dick Mattson
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 318-329

%T Monitoring Program Behaviour on SUPRENUM
%A Markus Siegle
%A Richard Hofmann
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 332-341

%T Dynamic Dependency Analysis of Ordinary Programs
%A Todd M. Austin
%A Gurindar S. Sohi
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 342-351

%T An Analysis of Loop Latency in Dataflow Execution
%A Walid A. Najjar
%A W. Marcus Miller
%A A. P. Wim Bohm
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 352-360

%T A Novel Cache Design for Vector Processing
%A Qing Yang
%A Liping Wu Yang
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 362-371

%T Increasing the Number of Strides for Conflict-Free Vector Access
%A Mateo Valero
%A Tomas Lang
%A Jose M. Llaberia
%A Montse Peiron
%A Eduard Ayguade
%A Juan J. Navarro
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 372-381

%T Evaluation of the WM Architecture
%A Wm. A. Wulf
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 382-390

%T The Impact of Communication Locality on Large-Scale Multiprocessor Performance
%A Kirk L. Johnson
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 392-402

%T Performance of the SCI Ring
%A Steven L. Scott
%A James R. Goodman
%A Mary K. Vernon
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 403-414

%T Tradeoffs in Supporting Two Page Sizes
%A Madhusudhan Talluri
%A Shing Kong
%A Mark D. Hill
%A David A. Patterson
%J Proc. 19th Annual Symposium on Computer Architecture
%D May 1992
%P 415-424