%Z -------------------------------------------------------------------------
%Z
%Z	Refer/bib bibliographic entries for the 14th
%Z	INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE
%Z	(1987) created by Julie Fingerson and Mark D. Hill
%Z 
%Z	These entries are correct to the best of our knowledge,
%Z	but we accept no responsibility for the consequences of
%Z	any errors.  Email corrections to hoffman@cs.wisc.edu.
%Z	Last change:  Tue Mar 28 15:51:01 CST 1995
%Z
%Z -------------------------------------------------------------------------
%Z

%T Branch Folding in the CRISP Microprocessor: Reducing Branch Delay to Zero
%A David R. Ditzel
%A Hubert R. McLellan
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 2-9

%T An Evaluation of Branch Architectures
%A John A. DeRosa
%A Henry M. Levy
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 10-16

%T Checkpoint Repair for Out-of-order Execution Machines
%A Wen-mei W. Hwu
%A Yale N. Patt
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 18-26

%T Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors
%A Gurindar S. Sohi
%A Sriram Vajapeyam 
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 27-34

%T Fast Temporary Storage for Serial and Parallel Execution
%A John Swensen
%A Yale Patt
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 35-43

%T Performance Analysis and Design of a Logic Simulation Machine
%A Ken Wong
%A Mark A. Franklin
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 46-55

%T A Modular Systolic Architecture for Image Convolutions
%A Kshitij Doshi
%A Peter Varman
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 56-63

%T A Template Matching Algorithm Using Optically-Connected 3-D VLSI Architecture
%A Satoshi Fujita
%A Reiji Aibara
%A Masafumi Yamashita
%A Tadashi Ae
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 64-70 

%T Mapping Data Flow Programs on a VLSI Array of Processors
%A Bilha Mendelson
%A Gabriel M. Silberman
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 72-80

%T Analytical Modeling and Architectural Modifications of a Dataflow Computer
%A Dipak Ghosal
%A Laxmi N. Bhuyan
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 81-89

%T A Unified Resource Management and Execution Control Mechanism for Data Flow Machines
%A Masaru Takesue
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 90-97

%T High Performance Integrated Prolog Processor IPP
%A S. Abe
%A T. Bandoh
%A S. Yamaguchi
%A K. Kurosawa
%A K. Kiriyama
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 100-107

%T Performance Studies of a Parallel Prolog Architecture
%A Barry S. Fagin
%A Alvin M. Despain
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 108-116

%T An Experimental VLSI Prolog Interpreter: Preliminary Measurements and Results
%A P. L. Civera
%A F. Maddaleno
%A G. L. Piccinini
%A M. Zamboni
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 117-126

%T Deterministic and Stochastic Modeling of Parallel Garbage Collection -- Towards Real-Time Criteria
%A Olivier Ridoux
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 128-136

%T The Sharing of Environment in AND-OR-Parallel Execution of Logic Programs
%A Sun Chengzheng
%A Tzu Yungui
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 137-144

%T Architectural Issues in Designing Symbolic Processors in Optics
%A Aloke Guha
%A Raja Ramnarayan
%A Matthew Derstine
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 145-151

%T Rearrangeability of Multistage Shuffle/Exchange Networks
%A Anujan Varma
%A C.S. Raghavendra
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 154-162

%T Optimized Mesh-Connected Networks for SIMD and MIMD Architectures
%A Ramon Beivide
%A Enrique Herrada
%A Jose L. Balcazar
%A Jesus Labarta
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 163-170

%T Performance Evaluation of Reduced Bandwidth Multistage Interconnection Networks
%A D. T. Harper III
%A J. R. Jump
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 171-175

%T Hardware Support for Interprocess Communication
%A Umakishore Ramachandran
%A Marvin Solomon
%A Mary Vernon
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 178-188 

%T Architecture of a Message-Driven Processor
%A William J. Dally
%A Linda Chao
%A Andrew Chien
%A Soha Hassoun
%A Waldemar Horwat
%A Jon Kaplan
%A Paul Song
%A Brian Totty
%A Scott Wills
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 189-196

%T Effect of Storage Allocation/Reclamation Methods on Parallelism and Storage Requirements
%A Manoj Kumar
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 197-205

%T Cache Design of a Sub-Micron CMOS System/370
%A J.H. Chang
%A H. Chao
%A K. So
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 208-213 

%T An Architectural Perspective on a Memory Access Controller
%A Martin Freeman
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 214-223

%T Organization and Analysis of a Gracefully-Degrading Interleaved Memory System
%A Kifung Cheung
%A Gurindar S. Sohi
%A Kewal Saluja
%A Dhiraj Pradham
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 224-231

%T Correct Memory Operation of Cache-Based Multiprocessors
%A Christoph Scheurich
%A Michel Dubois
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 234-243

%T Hierarchical Cache/Bus Architecture for Shared Memory Multiprocessors
%A Andrew W. Wilson Jr.
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 244-252

%T Multiprocessor Cache Design Considerations
%A Roland L. Lee
%A Pen-Chung Yew
%A Duncan H. Lawrie
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 253-262

%T Performance Evaluation of Multiple Register Sets
%A Richard J. Eickemeyer
%A Janak H. Patel
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 264-271

%T A Performance Analysis of Automatically Managed Top of Stack Buffers
%A Timothy J. Stanley
%A Robert G. Wedig
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 272-281

%T Concepts of the System/370 Vector Architecture
%A Brian Moore
%A Andris Padegs
%A Ron Smith
%A Werner Buchholz
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 282-288

%T WISQ: A Restartable Architecture Using Queues 
%A A. R. Pleszkun
%A J. R. Goodman
%A W-C. Hsu
%A R. T. Joersz
%A G. Bier
%A P. Woest
%A P. B. Schechter
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987 
%P 290-299

%T Architectural Tradeoffs in the Design of MIPS-X
%A Paul Chow
%A Mark Horowitz
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 300-308

%T The Hardware Architecture of the CRISP Microprocessor
%A David R.Ditzel
%A Hubert R. McLellan
%A Alan D. Berenbaum
%J Proc. 14th Annual Symposium on Computer Architecture
%D June 1987
%P 309-319